[PATCH] D119060: [InstCombine] SimplifyDemandedBits - mul(x, x) is odd iff x is odd

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri added inline comments.


================
Comment at: llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp:550-556
+        // X * X is odd iff X is odd.
+        if (DemandedMask == 1)
+          return I->getOperand(0);
+
+        // 'Quadratic Reciprocity': mul(x,x) -> 0 if we're only demanding bit[1]
+        if (DemandedMask == 2)
+          return ConstantInt::getNullValue(VTy);
----------------
Can we generalize this to something along the lines of:
if we only demand 2 low bits, then replace with `and %x, 0b00001` ?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D119060/new/

https://reviews.llvm.org/D119060