[llvm] 5372160 - [InstCombine] SimplifyDemandedBits - mul(x,x) - if only demand bit[1] then fold to zero

[Sanjay Patel via llvm-commits]

Author: Sanjay Patel
Date: 2022-02-05T09:51:38-05:00
New Revision: 5372160a188e3e0e84d09ba6a8353e39daefe4a0

URL: https://github.com/llvm/llvm-project/commit/5372160a188e3e0e84d09ba6a8353e39daefe4a0
DIFF: https://github.com/llvm/llvm-project/commit/5372160a188e3e0e84d09ba6a8353e39daefe4a0.diff

LOG: [InstCombine] SimplifyDemandedBits - mul(x,x) - if only demand bit[1] then fold to zero

This is a translation of the fold added to codegen with:
2d1390efbe61

Part of solving issue #48027

Added: 
    

Modified: 
    llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
    llvm/test/Transforms/InstCombine/mul-masked-bits.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
index baa7a74f481d9..d1640a02334b2 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
@@ -557,6 +557,9 @@ Value *InstCombinerImpl::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
         Instruction *Shl = BinaryOperator::CreateShl(I->getOperand(0), ShiftC);
         return InsertNewInstWith(Shl, *I);
       }
+      // 'Quadratic Reciprocity': mul(x,x) -> 0 if we're only demanding bit[1]
+      if (DemandedMask == 2 && I->getOperand(0) == I->getOperand(1))
+        return ConstantInt::getNullValue(VTy);
     }
     computeKnownBits(I, Known, Depth, CxtI);
     break;

diff  --git a/llvm/test/Transforms/InstCombine/mul-masked-bits.ll b/llvm/test/Transforms/InstCombine/mul-masked-bits.ll
index d872c7c9c8687..3f652ea807df0 100644
--- a/llvm/test/Transforms/InstCombine/mul-masked-bits.ll
+++ b/llvm/test/Transforms/InstCombine/mul-masked-bits.ll
@@ -22,10 +22,7 @@ define i32 @foo(i32 %x, i32 %y) {
 
 define i1 @PR48683(i32 %x) {
 ; CHECK-LABEL: @PR48683(
-; CHECK-NEXT:    [[A:%.*]] = mul i32 [[X:%.*]], [[X]]
-; CHECK-NEXT:    [[B:%.*]] = and i32 [[A]], 2
-; CHECK-NEXT:    [[C:%.*]] = icmp ne i32 [[B]], 0
-; CHECK-NEXT:    ret i1 [[C]]
+; CHECK-NEXT:    ret i1 false
 ;
   %a = mul i32 %x, %x
   %b = and i32 %a, 2
@@ -35,10 +32,7 @@ define i1 @PR48683(i32 %x) {
 
 define <4 x i1> @PR48683_vec(<4 x i32> %x) {
 ; CHECK-LABEL: @PR48683_vec(
-; CHECK-NEXT:    [[A:%.*]] = mul <4 x i32> [[X:%.*]], [[X]]
-; CHECK-NEXT:    [[B:%.*]] = and <4 x i32> [[A]], <i32 2, i32 2, i32 2, i32 2>
-; CHECK-NEXT:    [[C:%.*]] = icmp ne <4 x i32> [[B]], zeroinitializer
-; CHECK-NEXT:    ret <4 x i1> [[C]]
+; CHECK-NEXT:    ret <4 x i1> zeroinitializer
 ;
   %a = mul <4 x i32> %x, %x
   %b = and <4 x i32> %a, <i32 2, i32 2, i32 2, i32 2>