[llvm] 5f35009 - [RISCV] Remove a ComputeNumSignBits call from an isel special case.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2022-02-04T23:26:53-08:00
New Revision: 5f350099960c7615d8b0329fd3c251cbfd260407

URL: https://github.com/llvm/llvm-project/commit/5f350099960c7615d8b0329fd3c251cbfd260407
DIFF: https://github.com/llvm/llvm-project/commit/5f350099960c7615d8b0329fd3c251cbfd260407.diff

LOG: [RISCV] Remove a ComputeNumSignBits call from an isel special case.

Only isel (and (srl (sexti32 Y), c2), c1) -> (srliw (sraiw Y, 31), c3 - 32)
when there is a sext_inreg present. Don't both checking for Y
having 32 sign bits.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index c7173040175a8..bc0fde3f66632 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -734,11 +734,11 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
         //
         // This pattern occurs when (i32 (srl (sra 31), c3 - 32)) is type
         // legalized and goes through DAG combine.
-        SDValue Y;
         if (C2 >= 32 && (C3 - C2) == 1 && N0.hasOneUse() &&
-            selectSExti32(X, Y)) {
+            X.getOpcode() == ISD::SIGN_EXTEND_INREG &&
+            cast<VTSDNode>(X.getOperand(1))->getVT() == MVT::i32) {
           SDNode *SRAIW =
-              CurDAG->getMachineNode(RISCV::SRAIW, DL, XLenVT, Y,
+              CurDAG->getMachineNode(RISCV::SRAIW, DL, XLenVT, X.getOperand(0),
                                      CurDAG->getTargetConstant(31, DL, XLenVT));
           SDNode *SRLIW = CurDAG->getMachineNode(
               RISCV::SRLIW, DL, XLenVT, SDValue(SRAIW, 0),