[llvm] d752ea9 - [RISCV] Remove exclusions for zext.h/zext.w from our (and (srl X, C1), C2) selection code.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Fri Feb 4 17:15:23 PST 2022
Author: Craig Topper
Date: 2022-02-04T17:10:48-08:00
New Revision: d752ea9a7235cb0fe677517129e66b1935ae5285
URL: https://github.com/llvm/llvm-project/commit/d752ea9a7235cb0fe677517129e66b1935ae5285
DIFF: https://github.com/llvm/llvm-project/commit/d752ea9a7235cb0fe677517129e66b1935ae5285.diff
LOG: [RISCV] Remove exclusions for zext.h/zext.w from our (and (srl X, C1), C2) selection code.
This code tries to replace the pattern with a pair of shifts, but
we were excluding if the And could be a zext.h or zext.w. The SLLI/SRL
pair is more compressible and doesn't come with much down side.
We do regress one test case in rv64i-exhaustive-w-insts.ll but we
can probably add a narrower exclusion for that case.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
llvm/test/CodeGen/RISCV/rv64i-exhaustive-w-insts.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 02578fc82094b..c7173040175a8 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -700,13 +700,8 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
uint64_t C1 = N1C->getZExtValue();
- // Keep track of whether this is a andi, zext.h, or zext.w.
- bool ZExtOrANDI = isInt<12>(N1C->getSExtValue());
- if (C1 == UINT64_C(0xFFFF) &&
- (Subtarget->hasStdExtZbb() || Subtarget->hasStdExtZbp()))
- ZExtOrANDI = true;
- if (C1 == UINT64_C(0xFFFFFFFF) && Subtarget->hasStdExtZba())
- ZExtOrANDI = true;
+ // Keep track of whether this is an andi.
+ bool IsANDI = isInt<12>(N1C->getSExtValue());
// Clear irrelevant bits in the mask.
if (LeftShift)
@@ -753,7 +748,7 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
}
// (srli (slli x, c3-c2), c3).
- if (OneUseOrZExtW && !ZExtOrANDI) {
+ if (OneUseOrZExtW && !IsANDI) {
SDNode *SLLI = CurDAG->getMachineNode(
RISCV::SLLI, DL, XLenVT, X,
CurDAG->getTargetConstant(C3 - C2, DL, XLenVT));
@@ -783,7 +778,7 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
}
// (srli (slli c2+c3), c3)
- if (OneUseOrZExtW && !ZExtOrANDI) {
+ if (OneUseOrZExtW && !IsANDI) {
SDNode *SLLI = CurDAG->getMachineNode(
RISCV::SLLI, DL, XLenVT, X,
CurDAG->getTargetConstant(C2 + C3, DL, XLenVT));
@@ -801,7 +796,7 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
if (!LeftShift && isShiftedMask_64(C1)) {
uint64_t Leading = XLen - (64 - countLeadingZeros(C1));
uint64_t C3 = countTrailingZeros(C1);
- if (Leading == C2 && C2 + C3 < XLen && OneUseOrZExtW && !ZExtOrANDI) {
+ if (Leading == C2 && C2 + C3 < XLen && OneUseOrZExtW && !IsANDI) {
SDNode *SRLI = CurDAG->getMachineNode(
RISCV::SRLI, DL, XLenVT, X,
CurDAG->getTargetConstant(C2 + C3, DL, XLenVT));
@@ -813,7 +808,7 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
}
// If the leading zero count is C2+32, we can use SRLIW instead of SRLI.
if (Leading > 32 && (Leading - 32) == C2 && C2 + C3 < 32 &&
- OneUseOrZExtW && !ZExtOrANDI) {
+ OneUseOrZExtW && !IsANDI) {
SDNode *SRLIW = CurDAG->getMachineNode(
RISCV::SRLIW, DL, XLenVT, X,
CurDAG->getTargetConstant(C2 + C3, DL, XLenVT));
@@ -830,7 +825,7 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
if (LeftShift && isShiftedMask_64(C1)) {
uint64_t Leading = XLen - (64 - countLeadingZeros(C1));
uint64_t C3 = countTrailingZeros(C1);
- if (Leading == 0 && C2 < C3 && OneUseOrZExtW && !ZExtOrANDI) {
+ if (Leading == 0 && C2 < C3 && OneUseOrZExtW && !IsANDI) {
SDNode *SRLI = CurDAG->getMachineNode(
RISCV::SRLI, DL, XLenVT, X,
CurDAG->getTargetConstant(C3 - C2, DL, XLenVT));
@@ -841,7 +836,7 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
return;
}
// If we have (32-C2) leading zeros, we can use SRLIW instead of SRLI.
- if (C2 < C3 && Leading + C2 == 32 && OneUseOrZExtW && !ZExtOrANDI) {
+ if (C2 < C3 && Leading + C2 == 32 && OneUseOrZExtW && !IsANDI) {
SDNode *SRLIW = CurDAG->getMachineNode(
RISCV::SRLIW, DL, XLenVT, X,
CurDAG->getTargetConstant(C3 - C2, DL, XLenVT));
diff --git a/llvm/test/CodeGen/RISCV/rv64i-exhaustive-w-insts.ll b/llvm/test/CodeGen/RISCV/rv64i-exhaustive-w-insts.ll
index 7d5ec0e110791..777c814813cff 100644
--- a/llvm/test/CodeGen/RISCV/rv64i-exhaustive-w-insts.ll
+++ b/llvm/test/CodeGen/RISCV/rv64i-exhaustive-w-insts.ll
@@ -1766,49 +1766,31 @@ define signext i32 @sext_slliw_zext(i32 zeroext %a) nounwind {
; TODO: the constant shifts could be combined.
define zeroext i32 @zext_slliw_aext(i32 %a) nounwind {
-; RV64I-LABEL: zext_slliw_aext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: slli a0, a0, 39
-; RV64I-NEXT: srli a0, a0, 32
-; RV64I-NEXT: ret
-;
-; RV64ZBA-LABEL: zext_slliw_aext:
-; RV64ZBA: # %bb.0:
-; RV64ZBA-NEXT: slliw a0, a0, 7
-; RV64ZBA-NEXT: zext.w a0, a0
-; RV64ZBA-NEXT: ret
+; RV64-LABEL: zext_slliw_aext:
+; RV64: # %bb.0:
+; RV64-NEXT: slli a0, a0, 39
+; RV64-NEXT: srli a0, a0, 32
+; RV64-NEXT: ret
%1 = shl i32 %a, 7
ret i32 %1
}
define zeroext i32 @zext_slliw_sext(i32 signext %a) nounwind {
-; RV64I-LABEL: zext_slliw_sext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: slli a0, a0, 40
-; RV64I-NEXT: srli a0, a0, 32
-; RV64I-NEXT: ret
-;
-; RV64ZBA-LABEL: zext_slliw_sext:
-; RV64ZBA: # %bb.0:
-; RV64ZBA-NEXT: slliw a0, a0, 8
-; RV64ZBA-NEXT: zext.w a0, a0
-; RV64ZBA-NEXT: ret
+; RV64-LABEL: zext_slliw_sext:
+; RV64: # %bb.0:
+; RV64-NEXT: slli a0, a0, 40
+; RV64-NEXT: srli a0, a0, 32
+; RV64-NEXT: ret
%1 = shl i32 %a, 8
ret i32 %1
}
define zeroext i32 @zext_slliw_zext(i32 zeroext %a) nounwind {
-; RV64I-LABEL: zext_slliw_zext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: slli a0, a0, 41
-; RV64I-NEXT: srli a0, a0, 32
-; RV64I-NEXT: ret
-;
-; RV64ZBA-LABEL: zext_slliw_zext:
-; RV64ZBA: # %bb.0:
-; RV64ZBA-NEXT: slliw a0, a0, 9
-; RV64ZBA-NEXT: zext.w a0, a0
-; RV64ZBA-NEXT: ret
+; RV64-LABEL: zext_slliw_zext:
+; RV64: # %bb.0:
+; RV64-NEXT: slli a0, a0, 41
+; RV64-NEXT: srli a0, a0, 32
+; RV64-NEXT: ret
%1 = shl i32 %a, 9
ret i32 %1
}
@@ -1955,52 +1937,34 @@ define signext i32 @sext_sraiw_zext(i32 zeroext %a) nounwind {
; TODO: The sext.w+srli can be replaced with sraiw with Zba.
define zeroext i32 @zext_sraiw_aext(i32 %a) nounwind {
-; RV64I-LABEL: zext_sraiw_aext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: sext.w a0, a0
-; RV64I-NEXT: slli a0, a0, 25
-; RV64I-NEXT: srli a0, a0, 32
-; RV64I-NEXT: ret
-;
-; RV64ZBA-LABEL: zext_sraiw_aext:
-; RV64ZBA: # %bb.0:
-; RV64ZBA-NEXT: sraiw a0, a0, 7
-; RV64ZBA-NEXT: zext.w a0, a0
-; RV64ZBA-NEXT: ret
+; RV64-LABEL: zext_sraiw_aext:
+; RV64: # %bb.0:
+; RV64-NEXT: sext.w a0, a0
+; RV64-NEXT: slli a0, a0, 25
+; RV64-NEXT: srli a0, a0, 32
+; RV64-NEXT: ret
%1 = ashr i32 %a, 7
ret i32 %1
}
define zeroext i32 @zext_sraiw_sext(i32 signext %a) nounwind {
-; RV64I-LABEL: zext_sraiw_sext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: slli a0, a0, 24
-; RV64I-NEXT: srli a0, a0, 32
-; RV64I-NEXT: ret
-;
-; RV64ZBA-LABEL: zext_sraiw_sext:
-; RV64ZBA: # %bb.0:
-; RV64ZBA-NEXT: srli a0, a0, 8
-; RV64ZBA-NEXT: zext.w a0, a0
-; RV64ZBA-NEXT: ret
+; RV64-LABEL: zext_sraiw_sext:
+; RV64: # %bb.0:
+; RV64-NEXT: slli a0, a0, 24
+; RV64-NEXT: srli a0, a0, 32
+; RV64-NEXT: ret
%1 = ashr i32 %a, 8
ret i32 %1
}
; TODO: The sext.w+srli can be replaced with sraiw with Zba.
define zeroext i32 @zext_sraiw_zext(i32 zeroext %a) nounwind {
-; RV64I-LABEL: zext_sraiw_zext:
-; RV64I: # %bb.0:
-; RV64I-NEXT: sext.w a0, a0
-; RV64I-NEXT: slli a0, a0, 23
-; RV64I-NEXT: srli a0, a0, 32
-; RV64I-NEXT: ret
-;
-; RV64ZBA-LABEL: zext_sraiw_zext:
-; RV64ZBA: # %bb.0:
-; RV64ZBA-NEXT: sraiw a0, a0, 9
-; RV64ZBA-NEXT: zext.w a0, a0
-; RV64ZBA-NEXT: ret
+; RV64-LABEL: zext_sraiw_zext:
+; RV64: # %bb.0:
+; RV64-NEXT: sext.w a0, a0
+; RV64-NEXT: slli a0, a0, 23
+; RV64-NEXT: srli a0, a0, 32
+; RV64-NEXT: ret
%1 = ashr i32 %a, 9
ret i32 %1
}
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