[PATCH] D119010: [AggressiveInstCombine] Recognize table-based ctz implementation and enable it for AARCH64 at -O3

[Shubham Narlawar via Phabricator via llvm-commits]

gsocshubham created this revision.
gsocshubham added reviewers: momchil.velikov, KyrBoh, craig.topper, xbolva00, spatel, fhahn, lebedev.ri.
Herald added subscribers: hiraditya, kristof.beyls.
gsocshubham requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

This patch is improved version of patch https://reviews.llvm.org/D113291 submitted by @djtodoro
Credit goes to @djtodoro for his submission.

I have added fix in AArch64 backend and I have followed an approach suggested by @craig.topper here - 
https://github.com/llvm/llvm-project/issues/45779#issuecomment-1022851172

It generates below assembly -

  rbit    w8, w0
  clz     w8, w8
  and     w0, w8, #0x1f
  ret

which is similar assembly emitted by GCC AArch64 - https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90838

Patch fixes - https://github.com/llvm/llvm-project/issues/45779


https://reviews.llvm.org/D119010

Files:
  llvm/include/llvm/Analysis/TargetTransformInfo.h
  llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
  llvm/include/llvm/CodeGen/BasicTTIImpl.h
  llvm/include/llvm/CodeGen/TargetLowering.h
  llvm/lib/Analysis/TargetTransformInfo.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp
  llvm/test/Transforms/AggressiveInstCombine/AArch64/lit.local.cfg
  llvm/test/Transforms/AggressiveInstCombine/AArch64/lower-table-based-ctz.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D119010.405984.patch
Type: text/x-patch
Size: 15470 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20220204/af000d31/attachment.bin>