[PATCH] D119006: [AMDGPU] SILoadStoreOptimizer: avoid unbounded register pressure increases

[Jay Foad via Phabricator via llvm-commits]

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Previously when combining two loads this pass would sink the
first one down to the second one, putting the combined load
where the second one was. It would also sink any intervening
instructions which depended on the first load down to just
after the combined load.

For example, if we started with this sequence of
instructions (code flowing from left to right):

  X A B C D E F Y

After combining loads X and Y into XY we might end up with:

  A B C D E F XY

But if B D and F depended on X, we would get:

  A C E XY B D F

Now if the original code had some short disjoint live ranges
from A to B, C to D and E to F, in the transformed code
these live ranges will be long and overlapping. In this way
a single merge of two loads could cause an unbounded
increase in register pressure.

To fix this, change the way the way that loads are moved in
order to merge them so that:

- The second load is moved up to the first one. (But when merging stores, we still move the first store down to the second one.)
- Intervening instructions are never moved.
- Instead, if we find an intervening instruction that would need to be moved, give up on the merge. But this case should now be pretty rare because normal stores have no outputs, and normal loads only have address register inputs, but these will be identical for any pair of loads that we try to merge.

As well as fixing the unbounded register pressure increase
problem, moving loads up and stores down seems like it
should usually be a win for memory latency reasons.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D119006

Files:
  llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
  llvm/test/CodeGen/AMDGPU/ds-combine-with-dependence.ll
  llvm/test/CodeGen/AMDGPU/ds_read2.ll
  llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa.ll
  llvm/test/CodeGen/AMDGPU/merge-load-store-physreg.mir
  llvm/test/CodeGen/AMDGPU/merge-out-of-order-ldst.mir
  llvm/test/CodeGen/AMDGPU/merge-tbuffer.mir
  llvm/test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll

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