[PATCH] D119001: [x86] enable fast sqrtss tuning for AMD Zen cores

[Sanjay Patel via Phabricator via llvm-commits]

spatel created this revision.
spatel added reviewers: RKSimon, lebedev.ri, pengfei, craig.topper.
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As discussed in D118534 <https://reviews.llvm.org/D118534>, all of the recent AMD CPUs have relatively fast (<14 cycle latency) "sqrtss" instructions:
https://uops.info/table.html

So we should set this tuning flag to alter codegen of plain "sqrt(X)" expansion (as opposed to reciprocal-sqrt - there is other test coverage for that pattern). The expansion is both slower and less accurate than the hardware instruction.


https://reviews.llvm.org/D119001

Files:
  llvm/lib/Target/X86/X86.td
  llvm/test/CodeGen/X86/sqrt-fastmath-tune.ll


Index: llvm/test/CodeGen/X86/sqrt-fastmath-tune.ll
===================================================================
--- llvm/test/CodeGen/X86/sqrt-fastmath-tune.ll
+++ llvm/test/CodeGen/X86/sqrt-fastmath-tune.ll
@@ -3,8 +3,8 @@
 ; RUN: llc < %s -mtriple=x86_64-- -mcpu=sandybridge | FileCheck %s --check-prefixes=FAST-SCALAR,SNB
 ; RUN: llc < %s -mtriple=x86_64-- -mcpu=broadwell   | FileCheck %s --check-prefixes=FAST-SCALAR,BDW
 ; RUN: llc < %s -mtriple=x86_64-- -mcpu=skylake     | FileCheck %s --check-prefixes=FAST-SCALAR,SKL
-; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver1      | FileCheck %s --check-prefixes=SLOW-SCALAR,ZN1
-; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver3      | FileCheck %s --check-prefixes=SLOW-SCALAR,ZN3
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver1      | FileCheck %s --check-prefixes=FAST-SCALAR,ZN1
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver3      | FileCheck %s --check-prefixes=FAST-SCALAR,ZN3
 
 define float @f32_no_daz(float %f) #0 {
 ; NHM-LABEL: f32_no_daz:
@@ -26,19 +26,6 @@
 ; FAST-SCALAR:       # %bb.0:
 ; FAST-SCALAR-NEXT:    vsqrtss %xmm0, %xmm0, %xmm0
 ; FAST-SCALAR-NEXT:    retq
-;
-; SLOW-SCALAR-LABEL: f32_no_daz:
-; SLOW-SCALAR:       # %bb.0:
-; SLOW-SCALAR-NEXT:    vrsqrtss %xmm0, %xmm0, %xmm1
-; SLOW-SCALAR-NEXT:    vbroadcastss {{.*#+}} xmm3 = [NaN,NaN,NaN,NaN]
-; SLOW-SCALAR-NEXT:    vmulss %xmm1, %xmm0, %xmm2
-; SLOW-SCALAR-NEXT:    vfmadd213ss {{.*#+}} xmm1 = (xmm2 * xmm1) + mem
-; SLOW-SCALAR-NEXT:    vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
-; SLOW-SCALAR-NEXT:    vandps %xmm3, %xmm0, %xmm0
-; SLOW-SCALAR-NEXT:    vcmpltss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
-; SLOW-SCALAR-NEXT:    vmulss %xmm1, %xmm2, %xmm1
-; SLOW-SCALAR-NEXT:    vandnps %xmm1, %xmm0, %xmm0
-; SLOW-SCALAR-NEXT:    retq
   %call = tail call fast float @llvm.sqrt.f32(float %f) #2
   ret float %call
 }
@@ -256,18 +243,6 @@
 ; FAST-SCALAR:       # %bb.0:
 ; FAST-SCALAR-NEXT:    vsqrtss %xmm0, %xmm0, %xmm0
 ; FAST-SCALAR-NEXT:    retq
-;
-; SLOW-SCALAR-LABEL: f32_daz:
-; SLOW-SCALAR:       # %bb.0:
-; SLOW-SCALAR-NEXT:    vrsqrtss %xmm0, %xmm0, %xmm1
-; SLOW-SCALAR-NEXT:    vmulss %xmm1, %xmm0, %xmm2
-; SLOW-SCALAR-NEXT:    vfmadd213ss {{.*#+}} xmm1 = (xmm2 * xmm1) + mem
-; SLOW-SCALAR-NEXT:    vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
-; SLOW-SCALAR-NEXT:    vmulss %xmm1, %xmm2, %xmm1
-; SLOW-SCALAR-NEXT:    vxorps %xmm2, %xmm2, %xmm2
-; SLOW-SCALAR-NEXT:    vcmpeqss %xmm2, %xmm0, %xmm0
-; SLOW-SCALAR-NEXT:    vandnps %xmm1, %xmm0, %xmm0
-; SLOW-SCALAR-NEXT:    retq
   %call = tail call fast float @llvm.sqrt.f32(float %f) #2
   ret float %call
 }
Index: llvm/lib/Target/X86/X86.td
===================================================================
--- llvm/lib/Target/X86/X86.td
+++ llvm/lib/Target/X86/X86.td
@@ -1169,6 +1169,7 @@
                                      TuningFastBEXTR,
                                      TuningFast15ByteNOP,
                                      TuningBranchFusion,
+                                     TuningFastScalarFSQRT,
                                      TuningFastScalarShiftMasks,
                                      TuningFastMOVBE,
                                      TuningSlowSHLD,


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