[PATCH] D118302: [Spill2Reg] Code generation part 2.
Vasileios Porpodas via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Feb 3 15:56:57 PST 2022
vporpo added inline comments.
================
Comment at: llvm/lib/CodeGen/Spill2Reg.cpp:248
+ MachineInstr *SpillToVector = TII->spill2RegInsertToVectorReg(
+ VectorReg, OldReg, SpillData.MemBits, StackSpill->getParent(),
+ /*InsertBeforeIt=*/StackSpill->getIterator(), TRI);
----------------
arsenm wrote:
> Is this assuming you can only spill one register to one vector register? What if you can place multiple values in different subregisters?
Yes, for now we can only spill one register to the first lane of one vector register. The reason is that if we want to spill to another lane other than the first one in x86 then we need to use the PINSR/PEXTR instructions rather than MOVD which have a higher latency and use more uops. But yeah, I think it is still worth extending it to spill to more lanes in the future.
Here is the relevant data from Agner Fog's instruction tables:
```
uops uops uops
fused unfused each latency throughput
domain domain port
Spill-to-reg
------------
MOVD mm/x r32/64 1 1 p5 2 1
MOVD r32/64 mm/x 1 1 p0 2 1
PINSRD/Q x,r,i 2 2 2p5 3 2
PEXTRB/W/D/Q r,x,i 2 2 p0 p5 3 1
```
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D118302/new/
https://reviews.llvm.org/D118302
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