[PATCH] D118663: [AArch64] Adds SUBS and ADDS instructions to the MIPeepholeOpt.

[Micah Weston via Phabricator via llvm-commits]

red1bluelost marked 3 inline comments as done.
red1bluelost added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp:338
+    }
+    // Only valid if Condition Code is Equal or Not Equal
+    if (CC != AArch64CC::EQ && CC != AArch64CC::NE)
----------------
I scan the instructions which read NZCV after the Adds/Subs and check that the condition code is just EQ or NE.

These are the instructions that I that I was able to generate test cases for. Let me know if you think that there other instructions that I should add.


================
Comment at: llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp:393
+  MRI->constrainRegClass(SrcReg, ORC);
   MRI->constrainRegClass(NewTmpReg, ORC);
   MRI->constrainRegClass(NewDstReg, MRI->getRegClass(DstReg));
----------------
dmgreen wrote:
> This is technically assuming the two instructions have the same RegClass for Operand 1? I think that will always be the case, so maybe that's OK to keep as-is.
I added it just to be safe.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D118663/new/

https://reviews.llvm.org/D118663