[llvm] d3b87e4 - [AMDGPU] HWRegs TMA and TBA also supported on gfx9
Stanislav Mekhanoshin via llvm-commits
llvm-commits at lists.llvm.org
Thu Feb 3 09:36:17 PST 2022
Author: Stanislav Mekhanoshin
Date: 2022-02-03T09:36:10-08:00
New Revision: d3b87e4a1c5a433f13a6c694107659039a28b63f
URL: https://github.com/llvm/llvm-project/commit/d3b87e4a1c5a433f13a6c694107659039a28b63f
DIFF: https://github.com/llvm/llvm-project/commit/d3b87e4a1c5a433f13a6c694107659039a28b63f.diff
LOG: [AMDGPU] HWRegs TMA and TBA also supported on gfx9
Differential Revision: https://reviews.llvm.org/D118860
Added:
Modified:
llvm/lib/Target/AMDGPU/SIDefines.h
llvm/test/MC/AMDGPU/sopk-err.s
llvm/test/MC/AMDGPU/sopk.s
llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_all.txt
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/SIDefines.h b/llvm/lib/Target/AMDGPU/SIDefines.h
index 107ee5ed55325..494d2c77092f4 100644
--- a/llvm/lib/Target/AMDGPU/SIDefines.h
+++ b/llvm/lib/Target/AMDGPU/SIDefines.h
@@ -372,11 +372,11 @@ enum Id { // HwRegCode, (6) [5:0]
ID_MEM_BASES = 15,
ID_SYMBOLIC_FIRST_GFX9_ = ID_MEM_BASES,
ID_TBA_LO = 16,
- ID_SYMBOLIC_FIRST_GFX10_ = ID_TBA_LO,
ID_TBA_HI = 17,
ID_TMA_LO = 18,
ID_TMA_HI = 19,
ID_FLAT_SCR_LO = 20,
+ ID_SYMBOLIC_FIRST_GFX10_ = ID_FLAT_SCR_LO,
ID_FLAT_SCR_HI = 21,
ID_XNACK_MASK = 22,
ID_HW_ID1 = 23,
diff --git a/llvm/test/MC/AMDGPU/sopk-err.s b/llvm/test/MC/AMDGPU/sopk-err.s
index 95035836067d8..eb51d403bf43b 100644
--- a/llvm/test/MC/AMDGPU/sopk-err.s
+++ b/llvm/test/MC/AMDGPU/sopk-err.s
@@ -60,22 +60,22 @@ s_getreg_b32 s2, hwreg(HW_REG_SH_MEM_BASES)
s_getreg_b32 s2, hwreg(HW_REG_TBA_LO)
// GFX10: s_getreg_b32 s2, hwreg(HW_REG_TBA_LO) ; encoding: [0x10,0xf8,0x02,0xb9]
// SICIVI-ERR: error: specified hardware register is not supported on this GPU
-// GFX9-ERR: error: specified hardware register is not supported on this GPU
+// GFX9: s_getreg_b32 s2, hwreg(HW_REG_TBA_LO) ; encoding: [0x10,0xf8,0x82,0xb8]
s_getreg_b32 s2, hwreg(HW_REG_TBA_HI)
// GFX10: s_getreg_b32 s2, hwreg(HW_REG_TBA_HI) ; encoding: [0x11,0xf8,0x02,0xb9]
// SICIVI-ERR: error: specified hardware register is not supported on this GPU
-// GFX9-ERR: error: specified hardware register is not supported on this GPU
+// GFX9: s_getreg_b32 s2, hwreg(HW_REG_TBA_HI) ; encoding: [0x11,0xf8,0x82,0xb8]
s_getreg_b32 s2, hwreg(HW_REG_TMA_LO)
// GFX10: s_getreg_b32 s2, hwreg(HW_REG_TMA_LO) ; encoding: [0x12,0xf8,0x02,0xb9]
// SICIVI-ERR: error: specified hardware register is not supported on this GPU
-// GFX9-ERR: error: specified hardware register is not supported on this GPU
+// GFX9: s_getreg_b32 s2, hwreg(HW_REG_TMA_LO) ; encoding: [0x12,0xf8,0x82,0xb8]
s_getreg_b32 s2, hwreg(HW_REG_TMA_HI)
// GFX10: s_getreg_b32 s2, hwreg(HW_REG_TMA_HI) ; encoding: [0x13,0xf8,0x02,0xb9]
// SICIVI-ERR: error: specified hardware register is not supported on this GPU
-// GFX9-ERR: error: specified hardware register is not supported on this GPU
+// GFX9: s_getreg_b32 s2, hwreg(HW_REG_TMA_HI) ; encoding: [0x13,0xf8,0x82,0xb8]
s_getreg_b32 s2, hwreg(HW_REG_FLAT_SCR_LO)
// GFX10: s_getreg_b32 s2, hwreg(HW_REG_FLAT_SCR_LO) ; encoding: [0x14,0xf8,0x02,0xb9]
diff --git a/llvm/test/MC/AMDGPU/sopk.s b/llvm/test/MC/AMDGPU/sopk.s
index d186d9bb128b5..75c27fa11e53c 100644
--- a/llvm/test/MC/AMDGPU/sopk.s
+++ b/llvm/test/MC/AMDGPU/sopk.s
@@ -153,27 +153,31 @@ s_getreg_b32 s2, hwreg(15)
// GFX9: s_getreg_b32 s2, hwreg(HW_REG_SH_MEM_BASES) ; encoding: [0x0f,0xf8,0x82,0xb8]
// GFX10: s_getreg_b32 s2, hwreg(HW_REG_SH_MEM_BASES) ; encoding: [0x0f,0xf8,0x02,0xb9]
-// GFX10+ registers
s_getreg_b32 s2, hwreg(16)
// SICI: s_getreg_b32 s2, hwreg(16) ; encoding: [0x10,0xf8,0x02,0xb9]
-// VI9: s_getreg_b32 s2, hwreg(16) ; encoding: [0x10,0xf8,0x82,0xb8]
+// VI: s_getreg_b32 s2, hwreg(16) ; encoding: [0x10,0xf8,0x82,0xb8]
+// GFX9: s_getreg_b32 s2, hwreg(HW_REG_TBA_LO) ; encoding: [0x10,0xf8,0x82,0xb8]
// GFX10: s_getreg_b32 s2, hwreg(HW_REG_TBA_LO) ; encoding: [0x10,0xf8,0x02,0xb9]
s_getreg_b32 s2, hwreg(17)
// SICI: s_getreg_b32 s2, hwreg(17) ; encoding: [0x11,0xf8,0x02,0xb9]
-// VI9: s_getreg_b32 s2, hwreg(17) ; encoding: [0x11,0xf8,0x82,0xb8]
+// VI: s_getreg_b32 s2, hwreg(17) ; encoding: [0x11,0xf8,0x82,0xb8]
+// GFX9: s_getreg_b32 s2, hwreg(HW_REG_TBA_HI) ; encoding: [0x11,0xf8,0x82,0xb8]
// GFX10: s_getreg_b32 s2, hwreg(HW_REG_TBA_HI) ; encoding: [0x11,0xf8,0x02,0xb9]
s_getreg_b32 s2, hwreg(18)
// SICI: s_getreg_b32 s2, hwreg(18) ; encoding: [0x12,0xf8,0x02,0xb9]
-// VI9: s_getreg_b32 s2, hwreg(18) ; encoding: [0x12,0xf8,0x82,0xb8]
+// VI: s_getreg_b32 s2, hwreg(18) ; encoding: [0x12,0xf8,0x82,0xb8]
+// GFX9: s_getreg_b32 s2, hwreg(HW_REG_TMA_LO) ; encoding: [0x12,0xf8,0x82,0xb8]
// GFX10: s_getreg_b32 s2, hwreg(HW_REG_TMA_LO) ; encoding: [0x12,0xf8,0x02,0xb9]
s_getreg_b32 s2, hwreg(19)
// SICI: s_getreg_b32 s2, hwreg(19) ; encoding: [0x13,0xf8,0x02,0xb9]
-// VI9: s_getreg_b32 s2, hwreg(19) ; encoding: [0x13,0xf8,0x82,0xb8]
+// VI: s_getreg_b32 s2, hwreg(19) ; encoding: [0x13,0xf8,0x82,0xb8]
+// GFX9: s_getreg_b32 s2, hwreg(HW_REG_TMA_HI) ; encoding: [0x13,0xf8,0x82,0xb8]
// GFX10: s_getreg_b32 s2, hwreg(HW_REG_TMA_HI) ; encoding: [0x13,0xf8,0x02,0xb9]
+// GFX10+ registers
s_getreg_b32 s2, hwreg(20)
// SICI: s_getreg_b32 s2, hwreg(20) ; encoding: [0x14,0xf8,0x02,0xb9]
// VI9: s_getreg_b32 s2, hwreg(20) ; encoding: [0x14,0xf8,0x82,0xb8]
@@ -257,27 +261,31 @@ s_setreg_b32 hwreg(15), s2
// GFX9: s_setreg_b32 hwreg(HW_REG_SH_MEM_BASES), s2 ; encoding: [0x0f,0xf8,0x02,0xb9]
// GFX10: s_setreg_b32 hwreg(HW_REG_SH_MEM_BASES), s2 ; encoding: [0x0f,0xf8,0x82,0xb9]
-// GFX10+ registers
s_setreg_b32 hwreg(16), s2
// SICI: s_setreg_b32 hwreg(16), s2 ; encoding: [0x10,0xf8,0x82,0xb9]
-// VI9: s_setreg_b32 hwreg(16), s2 ; encoding: [0x10,0xf8,0x02,0xb9]
+// VI: s_setreg_b32 hwreg(16), s2 ; encoding: [0x10,0xf8,0x02,0xb9]
+// GFX9: s_setreg_b32 hwreg(HW_REG_TBA_LO), s2 ; encoding: [0x10,0xf8,0x02,0xb9]
// GFX10: s_setreg_b32 hwreg(HW_REG_TBA_LO), s2 ; encoding: [0x10,0xf8,0x82,0xb9]
s_setreg_b32 hwreg(17), s2
// SICI: s_setreg_b32 hwreg(17), s2 ; encoding: [0x11,0xf8,0x82,0xb9]
-// VI9: s_setreg_b32 hwreg(17), s2 ; encoding: [0x11,0xf8,0x02,0xb9]
+// VI: s_setreg_b32 hwreg(17), s2 ; encoding: [0x11,0xf8,0x02,0xb9]
+// GFX9: s_setreg_b32 hwreg(HW_REG_TBA_HI), s2 ; encoding: [0x11,0xf8,0x02,0xb9]
// GFX10: s_setreg_b32 hwreg(HW_REG_TBA_HI), s2 ; encoding: [0x11,0xf8,0x82,0xb9]
s_setreg_b32 hwreg(18), s2
// SICI: s_setreg_b32 hwreg(18), s2 ; encoding: [0x12,0xf8,0x82,0xb9]
-// VI9: s_setreg_b32 hwreg(18), s2 ; encoding: [0x12,0xf8,0x02,0xb9]
+// VI: s_setreg_b32 hwreg(18), s2 ; encoding: [0x12,0xf8,0x02,0xb9]
+// GFX9: s_setreg_b32 hwreg(HW_REG_TMA_LO), s2 ; encoding: [0x12,0xf8,0x02,0xb9]
// GFX10: s_setreg_b32 hwreg(HW_REG_TMA_LO), s2 ; encoding: [0x12,0xf8,0x82,0xb9]
s_setreg_b32 hwreg(19), s2
// SICI: s_setreg_b32 hwreg(19), s2 ; encoding: [0x13,0xf8,0x82,0xb9]
-// VI9: s_setreg_b32 hwreg(19), s2 ; encoding: [0x13,0xf8,0x02,0xb9]
+// VI: s_setreg_b32 hwreg(19), s2 ; encoding: [0x13,0xf8,0x02,0xb9]
+// GFX9: s_setreg_b32 hwreg(HW_REG_TMA_HI), s2 ; encoding: [0x13,0xf8,0x02,0xb9]
// GFX10: s_setreg_b32 hwreg(HW_REG_TMA_HI), s2 ; encoding: [0x13,0xf8,0x82,0xb9]
+// GFX10+ registers
s_setreg_b32 hwreg(20), s2
// SICI: s_setreg_b32 hwreg(20), s2 ; encoding: [0x14,0xf8,0x82,0xb9]
// VI9: s_setreg_b32 hwreg(20), s2 ; encoding: [0x14,0xf8,0x02,0xb9]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_all.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_all.txt
index a39a25e8be46d..3924a902b4d9c 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_all.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_all.txt
@@ -20406,13 +20406,13 @@
# CHECK: s_getreg_b32 exec_hi, hwreg(HW_REG_MODE, 5, 7) ; encoding: [0x41,0x31,0xff,0xb8]
0x41,0x31,0xff,0xb8
-# CHECK: s_getreg_b32 s5, hwreg(17, 7, 25) ; encoding: [0xd1,0xc1,0x85,0xb8]
+# CHECK: s_getreg_b32 s5, hwreg(HW_REG_TBA_HI, 7, 25) ; encoding: [0xd1,0xc1,0x85,0xb8]
0xd1,0xc1,0x85,0xb8
# CHECK: s_setreg_b32 hwreg(HW_REG_MODE, 5, 7), s1 ; encoding: [0x41,0x31,0x01,0xb9]
0x41,0x31,0x01,0xb9
-# CHECK: s_setreg_b32 hwreg(17, 7, 25), s1 ; encoding: [0xd1,0xc1,0x01,0xb9]
+# CHECK: s_setreg_b32 hwreg(HW_REG_TBA_HI, 7, 25), s1 ; encoding: [0xd1,0xc1,0x01,0xb9]
0xd1,0xc1,0x01,0xb9
# CHECK: s_setreg_b32 hwreg(HW_REG_MODE, 5, 7), s101 ; encoding: [0x41,0x31,0x65,0xb9]
@@ -20442,7 +20442,7 @@
# CHECK: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 5, 7), 0x11213141 ; encoding: [0x41,0x31,0x00,0xba,0x41,0x31,0x21,0x11]
0x41,0x31,0x00,0xba,0x41,0x31,0x21,0x11
-# CHECK: s_setreg_imm32_b32 hwreg(17, 7, 25), 0x11213141 ; encoding: [0xd1,0xc1,0x00,0xba,0x41,0x31,0x21,0x11]
+# CHECK: s_setreg_imm32_b32 hwreg(HW_REG_TBA_HI, 7, 25), 0x11213141 ; encoding: [0xd1,0xc1,0x00,0xba,0x41,0x31,0x21,0x11]
0xd1,0xc1,0x00,0xba,0x41,0x31,0x21,0x11
# CHECK: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 5, 7), 0xa1b1c1d1 ; encoding: [0x41,0x31,0x00,0xba,0xd1,0xc1,0xb1,0xa1]
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