[PATCH] D118602: [CodeGenPrepare] Avoid out-of-bounds shift

[Sanjay Patel via Phabricator via llvm-commits]

spatel added a comment.

This seems fine, but check my understanding: there's no difference in the test output with this fix if opt is not built with ubsan enabled?

Could/should we just exit if we detect malformed IR?

  diff --git a/llvm/lib/CodeGen/CodeGenPrepare.cpp b/llvm/lib/CodeGen/CodeGenPrepare.cpp
  index c888adeafca5..294a37689013 100644
  --- a/llvm/lib/CodeGen/CodeGenPrepare.cpp
  +++ b/llvm/lib/CodeGen/CodeGenPrepare.cpp
  @@ -4551,9 +4551,12 @@ bool AddressingModeMatcher::matchOperationAddr(User *AddrInst, unsigned Opcode,
       if (!RHS || RHS->getBitWidth() > 64)
         return false;
       int64_t Scale = RHS->getSExtValue();
  -    if (Opcode == Instruction::Shl)
  +    if (Opcode == Instruction::Shl) {
  +      // Bail out if the IR is not well-defined (overshift is poison).
  +      if (RHS->getZExtValue() > 63)
  +        return false;
         Scale = 1LL << Scale;
  -
  +    }
       return matchScaledValue(AddrInst->getOperand(0), Scale, Depth);
     }
     case Instruction::GetElementPtr: {


Repository:
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  https://reviews.llvm.org/D118602/new/

https://reviews.llvm.org/D118602