[PATCH] D118617: [AArch64][SVE] Remove false register dependency for unary FP convert operations

[Peter Waller via Phabricator via llvm-commits]

peterwaller-arm added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td:1685
   // Floating-point -> signed integer
-  def : Pat<(nxv2f16 (AArch64scvtf_mt (nxv2i1 PPR:$Pg),
+  def : Pat<(nxv2f16 (AArch64scvtf_mt (nxv2i1 (SVEAllActive):$Pg),
                       (sext_inreg (nxv2i64 ZPR:$Zs), nxv2i16), (nxv2f16 ZPR:$Zd))),
----------------
bsmith wrote:
> I don't believe converting these patterns like this is ok, some of the intrinsics (such as `@llvm.aarch64.sve.scvtf`) can get lowered to these nodes without an all active predicate. With this patch I believe a case such as the below will either regress or fail to select.
> 
> ```
> define <vscale x 8 x half> @scvtf_f16_i16(<vscale x 8 x half> %a, <vscale x 8 x i1> %pg, <vscale x 8 x i16> %b) {
>     %out = call <vscale x 8 x half> @llvm.aarch64.sve.scvtf.nxv8f16.nxv8i16(<vscale x 8 x half> %a,<vscale x 8 x i1> %pg, <vscale x 8 x i16> %b)
>    ret <vscale x 8 x half> %out
> }
> 
> declare <vscale x 8 x half> @llvm.aarch64.sve.scvtf.nxv8f16.nxv8i16(<vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x i16>)
> ```
These patterns exist to improve the code quality for the unpacked types (e.g. `<vscale x 2 x i16>`), and those are not expressible by the user (via the intrinsics). The predicate is all true by construction -- via the IR instructions -- so we have realised that the `_UNDEF` forms are what is wanted here, and these patterns are only needed for the `(SVEAllActive)` case.


Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D118617/new/

https://reviews.llvm.org/D118617