[PATCH] D118461: [AMDGPU] Introduce new ISel combine for trunc-slr patterns

[Thomas Symalla via Phabricator via llvm-commits]

tsymalla added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/SIInstructions.td:2290
+// v_and_b32_e64 $a, (1 << $b), $a
+// v_cmp_eq_u32_e64 $a, (1 << $b), $a 
+
----------------
foad wrote:
> foad wrote:
> > `v_cmp_ne_u32_e64 $a, 0, $a` is probably better because 0 is always an inline constant, but `1 << $b` might not be.
> Also, if you do this, there will only be one use of the constant not two, so I don't think you will have to "Restrict the range to prevent using an additional VGPR for the shifted value".
The resulting value should still be checked to ensure no 32-bit overflow occurs, correct? For instance, if the shift value is something like 33, 1 << 33 would exceed Int32_Max.


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  https://reviews.llvm.org/D118461/new/

https://reviews.llvm.org/D118461