[PATCH] D118845: [RISCV] Move the creation of VLMaxSentinel to isel. Use X0 during lowering.
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 2 13:23:50 PST 2022
craig.topper created this revision.
craig.topper added reviewers: frasercrmck, rogfer01.
Herald added subscribers: VincentWu, luke957, achieveartificialintelligence, vkmr, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, edward-jones, zzheng, jrtc27, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, hiraditya.
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Herald added subscribers: pcwang-thead, eopXD, MaskRay.
Herald added a project: LLVM.
The VLMaxSentinel is represented as TargetConstant, but that's included
in isa<ConstantSDNode>. To keep constant VLs and VLMax separate as long
as possible use the X0 register during lowering and only convert to
VLMaxSentinel during isel.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D118845
Files:
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
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