[PATCH] D118345: [AArch64][SVE] Add more folds to make use of gather/scatter with 32-bit indices

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen added a comment.

Just a few final comments, otherwise looks fine to me.



================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:16181
+      Index.getOperand(0).getOpcode() == ISD::ADD &&
+      Index.getOperand(0).getOperand(0).getOpcode() == ISD::STEP_VECTOR) {
+    if (auto *Shift = dyn_cast_or_null<ConstantSDNode>(
----------------
I'd suggest creating some variables here, so that further on you don't need to write something like:

  Index.getOperand(0).getOperand(0).getOperand(0)

Instead, if you create some variables:

  SDValue Add = Index.getOperand(0);
  SDValue ShiftOp = Index.getOperand(1);
  SDValue StepOp = Add.getOperand(0);
  SDValue OffsetOp = Add.getOperand(1);

Then the code below becomes a bit more readable:

  if (auto *Shift = dyn_cast_or_null<ConstantSDNode>(DAG.getSplatValue(ShiftOp))) {
    if (SDValue Offset = DAG.getSplatValue(OffsetOp)) {
      int64_t Step = cast<ConstantSDNode>(StepOp.getOperand(0))->getSExtValue();
      ...
    }
  }



================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:16190
+                           ->getSExtValue();
+        // Stride does not scaled explicitly by 'Scale', because it happens in
+        // the gather/scatter addressing mode.
----------------
nit: s/scaled/scale/


Repository:
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https://reviews.llvm.org/D118345