[PATCH] D118802: [AArch64][CodeGen] Always use SVE (when enabled) to lower 64-bit vector multiplies

[David Sherwood via Phabricator via llvm-commits]

david-arm created this revision.
david-arm added reviewers: sdesmalen, paulwalker-arm, peterwaller-arm, kmclaughlin.
Herald added subscribers: ctetreau, hiraditya, kristof.beyls, tschuett.
david-arm requested review of this revision.
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This patch adds custom lowering support for ISD::MUL with v1i64 and v2i64
types when SVE is enabled, regardless of the minimum SVE vector length. We
do this because NEON simply does not have 64-bit vector multiplies, so we
want to take advantage of these instructions in SVE.

I've updated the 128-bit min SVE vector bits tests here:

  CodeGen/AArch64/sve-fixed-length-int-arith.ll
  CodeGen/AArch64/sve-fixed-length-int-mulh.ll
  CodeGen/AArch64/sve-fixed-length-int-rem.ll


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D118802

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-arith.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-mulh.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-rem.ll

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