[llvm] 73cb542 - [NFC][SimplifyCFG] Autogenerate checklines in a few tests being affected by upcoming change
Roman Lebedev via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 2 06:54:24 PST 2022
Author: Roman Lebedev
Date: 2022-02-02T17:53:56+03:00
New Revision: 73cb542930bb28424aea4329a43de11b5b3a6761
URL: https://github.com/llvm/llvm-project/commit/73cb542930bb28424aea4329a43de11b5b3a6761
DIFF: https://github.com/llvm/llvm-project/commit/73cb542930bb28424aea4329a43de11b5b3a6761.diff
LOG: [NFC][SimplifyCFG] Autogenerate checklines in a few tests being affected by upcoming change
Added:
Modified:
llvm/test/Transforms/SimplifyCFG/UnreachableEliminate.ll
llvm/test/Transforms/SimplifyCFG/X86/sink-common-code.ll
llvm/test/Transforms/SimplifyCFG/bbi-23595.ll
llvm/test/Transforms/SimplifyCFG/no-md-sink.ll
llvm/test/Transforms/SimplifyCFG/preserve-store-alignment.ll
Removed:
################################################################################
diff --git a/llvm/test/Transforms/SimplifyCFG/UnreachableEliminate.ll b/llvm/test/Transforms/SimplifyCFG/UnreachableEliminate.ll
index 0d6b941bb84f6..824f6b92e8807 100644
--- a/llvm/test/Transforms/SimplifyCFG/UnreachableEliminate.ll
+++ b/llvm/test/Transforms/SimplifyCFG/UnreachableEliminate.ll
@@ -95,8 +95,8 @@ define void @test5_type_test_assume(i1 %cond, i8* %ptr, [3 x i8*]* %vtable) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = xor i1 [[COND:%.*]], true
; CHECK-NEXT: call void @llvm.assume(i1 [[TMP0]])
-; CHECK-NEXT: [[VTABLE:%.*]] = bitcast [3 x i8*]* %vtable to i8*
-; CHECK-NEXT: [[P:%.*]] = call i1 @llvm.type.test(i8* [[VTABLE]], metadata !"foo")
+; CHECK-NEXT: [[VTABLEI8:%.*]] = bitcast [3 x i8*]* [[VTABLE:%.*]] to i8*
+; CHECK-NEXT: [[P:%.*]] = call i1 @llvm.type.test(i8* [[VTABLEI8]], metadata !"foo")
; CHECK-NEXT: tail call void @llvm.assume(i1 [[P]])
; CHECK-NEXT: store i8 2, i8* [[PTR:%.*]], align 8
; CHECK-NEXT: ret void
@@ -122,8 +122,8 @@ bb2:
define void @test5_no_null_opt(i1 %cond, i8* %ptr) #0 {
; CHECK-LABEL: @test5_no_null_opt(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[PTR_2:%.*]] = select i1 [[COND:%.*]], i8* null, i8* [[PTR:%.*]]
-; CHECK-NEXT: store i8 2, i8* [[PTR_2]], align 8
+; CHECK-NEXT: [[DOTPTR:%.*]] = select i1 [[COND:%.*]], i8* null, i8* [[PTR:%.*]]
+; CHECK-NEXT: store i8 2, i8* [[DOTPTR]], align 8
; CHECK-NEXT: ret void
;
entry:
diff --git a/llvm/test/Transforms/SimplifyCFG/X86/sink-common-code.ll b/llvm/test/Transforms/SimplifyCFG/X86/sink-common-code.ll
index 5ccd6e5899a72..2ac555ca0caaa 100644
--- a/llvm/test/Transforms/SimplifyCFG/X86/sink-common-code.ll
+++ b/llvm/test/Transforms/SimplifyCFG/X86/sink-common-code.ll
@@ -1256,28 +1256,28 @@ merge:
}
-%T = type {i32, i32}
+%TP = type {i32, i32}
-define i32 @test_insertvalue(i1 zeroext %flag, %T %P) {
+define i32 @test_insertvalue(i1 zeroext %flag, %TP %P) {
; CHECK-LABEL: @test_insertvalue(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[DOT:%.*]] = select i1 [[FLAG:%.*]], i32 0, i32 1
-; CHECK-NEXT: [[T2:%.*]] = insertvalue [[T:%.*]] [[P:%.*]], i32 [[DOT]], 0
+; CHECK-NEXT: [[I2:%.*]] = insertvalue [[TP:%.*]] [[P:%.*]], i32 [[DOT]], 0
; CHECK-NEXT: ret i32 1
;
entry:
br i1 %flag, label %if.then, label %if.else
if.then:
- %t1 = insertvalue %T %P, i32 0, 0
+ %i1 = insertvalue %TP %P, i32 0, 0
br label %if.end
if.else:
- %t2 = insertvalue %T %P, i32 1, 0
+ %i2 = insertvalue %TP %P, i32 1, 0
br label %if.end
if.end:
- %t = phi %T [%t1, %if.then], [%t2, %if.else]
+ %i = phi %TP [%i1, %if.then], [%i2, %if.else]
ret i32 1
}
diff --git a/llvm/test/Transforms/SimplifyCFG/bbi-23595.ll b/llvm/test/Transforms/SimplifyCFG/bbi-23595.ll
index b09f04d841ca9..2076ce50e98fe 100644
--- a/llvm/test/Transforms/SimplifyCFG/bbi-23595.ll
+++ b/llvm/test/Transforms/SimplifyCFG/bbi-23595.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -S -simplifycfg -simplifycfg-require-and-preserve-domtree=1 | FileCheck %s
; In 'simplifycfg', during the flattening of a 'br', the instructions for the
@@ -10,12 +11,12 @@
; We're expecting the dbg.label associated with 'W' to disappear, because
; the 'W' label was removed.
-; CHECK-LABEL: _Z7test_itv()
-; CHECK: entry:
-; CHECK-NEXT: %retval.0 = select i1 undef, i16 1, i16 0
-; CHECK-NEXT: ret i16 0
-
define i16 @_Z7test_itv() {
+; CHECK-LABEL: @_Z7test_itv(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[RETVAL_0:%.*]] = select i1 undef, i16 1, i16 0
+; CHECK-NEXT: ret i16 0
+;
entry:
br label %sw.bb
diff --git a/llvm/test/Transforms/SimplifyCFG/no-md-sink.ll b/llvm/test/Transforms/SimplifyCFG/no-md-sink.ll
index 3444ce96ada05..4d54c05d05b22 100644
--- a/llvm/test/Transforms/SimplifyCFG/no-md-sink.ll
+++ b/llvm/test/Transforms/SimplifyCFG/no-md-sink.ll
@@ -1,7 +1,15 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -sink-common-insts -S | FileCheck %s
; RUN: opt < %s -passes='simplifycfg<sink-common-insts>' -S | FileCheck %s
define i1 @test1(i1 zeroext %flag, i8* %y) #0 {
+; CHECK-LABEL: @test1(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[S:%.*]] = call i1 @llvm.type.test(i8* [[Y:%.*]], metadata [[META0:![0-9]+]])
+; CHECK-NEXT: [[R:%.*]] = call i1 @llvm.type.test(i8* [[Y]], metadata [[META1:![0-9]+]])
+; CHECK-NEXT: [[T:%.*]] = select i1 [[FLAG:%.*]], i1 [[R]], i1 [[S]]
+; CHECK-NEXT: ret i1 [[T]]
+;
entry:
br i1 %flag, label %if.then, label %if.else
@@ -23,12 +31,13 @@ if.end:
declare i1 @llvm.type.test(i8* %ptr, metadata %bitset) nounwind readnone
-; CHECK-LABEL: test1
-; CHECK: @llvm.type.test
-; CHECK: @llvm.type.test
-; CHECK: ret i1
-
define i1 @test2(i1 zeroext %flag, i8* %y, i8* %z) #0 {
+; CHECK-LABEL: @test2(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[Y_Z:%.*]] = select i1 [[FLAG:%.*]], i8* [[Y:%.*]], i8* [[Z:%.*]]
+; CHECK-NEXT: [[S:%.*]] = call i1 @llvm.type.test(i8* [[Y_Z]], metadata [[META1]])
+; CHECK-NEXT: ret i1 [[S]]
+;
entry:
br i1 %flag, label %if.then, label %if.else
@@ -44,9 +53,3 @@ if.end:
%t = phi i1 [ %s, %if.else ], [ %r, %if.then ]
ret i1 %t
}
-
-; CHECK-LABEL: test2
-; CHECK: %[[S:[a-z0-9.]+]] = select i1 %flag, i8* %y, i8* %z
-; CHECK: %[[R:[a-z0-9.]+]] = call i1 @llvm.type.test(i8* %[[S]], metadata ![[MD:[0-9]+]]
-; CHECK: ret i1 %[[R]]
-; CHECK: ![[MD]] = !{i32 0, !"typeid1"}
diff --git a/llvm/test/Transforms/SimplifyCFG/preserve-store-alignment.ll b/llvm/test/Transforms/SimplifyCFG/preserve-store-alignment.ll
index 32ec6f751599b..bf77c36d39d7c 100644
--- a/llvm/test/Transforms/SimplifyCFG/preserve-store-alignment.ll
+++ b/llvm/test/Transforms/SimplifyCFG/preserve-store-alignment.ll
@@ -20,13 +20,13 @@ define i32 @align_both_equal() local_unnamed_addr {
; CHECK-NEXT: [[AND4:%.*]] = and i64 [[TMP2]], 2
; CHECK-NEXT: [[TOBOOL5:%.*]] = icmp eq i64 [[AND4]], 0
; CHECK-NEXT: [[TMP5:%.*]] = add nsw <2 x i64> [[TMP4]], <i64 1, i64 1>
-; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[TOBOOL5]], <2 x i64> [[TMP4]], <2 x i64> [[TMP5]]
+; CHECK-NEXT: [[SIMPLIFYCFG_MERGE:%.*]] = select i1 [[TOBOOL5]], <2 x i64> [[TMP4]], <2 x i64> [[TMP5]]
; CHECK-NEXT: [[TMP6:%.*]] = xor i1 [[TOBOOL]], true
; CHECK-NEXT: [[TMP7:%.*]] = xor i1 [[TOBOOL5]], true
; CHECK-NEXT: [[TMP8:%.*]] = or i1 [[TMP6]], [[TMP7]]
; CHECK-NEXT: br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP10:%.*]]
; CHECK: 9:
-; CHECK-NEXT: store <2 x i64> [[SPEC_SELECT]], <2 x i64>* bitcast (i64* getelementptr inbounds ([[STRUCT_COUNTERS]], %struct.Counters* @counters, i64 0, i32 1) to <2 x i64>*), align 8
+; CHECK-NEXT: store <2 x i64> [[SIMPLIFYCFG_MERGE]], <2 x i64>* bitcast (i64* getelementptr inbounds ([[STRUCT_COUNTERS]], %struct.Counters* @counters, i64 0, i32 1) to <2 x i64>*), align 8
; CHECK-NEXT: br label [[TMP10]]
; CHECK: 10:
; CHECK-NEXT: ret i32 0
@@ -74,13 +74,13 @@ define i32 @align_not_equal() local_unnamed_addr {
; CHECK-NEXT: [[AND4:%.*]] = and i64 [[TMP2]], 2
; CHECK-NEXT: [[TOBOOL5:%.*]] = icmp eq i64 [[AND4]], 0
; CHECK-NEXT: [[TMP5:%.*]] = add nsw <2 x i64> [[TMP4]], <i64 1, i64 1>
-; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[TOBOOL5]], <2 x i64> [[TMP4]], <2 x i64> [[TMP5]]
+; CHECK-NEXT: [[SIMPLIFYCFG_MERGE:%.*]] = select i1 [[TOBOOL5]], <2 x i64> [[TMP4]], <2 x i64> [[TMP5]]
; CHECK-NEXT: [[TMP6:%.*]] = xor i1 [[TOBOOL]], true
; CHECK-NEXT: [[TMP7:%.*]] = xor i1 [[TOBOOL5]], true
; CHECK-NEXT: [[TMP8:%.*]] = or i1 [[TMP6]], [[TMP7]]
; CHECK-NEXT: br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP10:%.*]]
; CHECK: 9:
-; CHECK-NEXT: store <2 x i64> [[SPEC_SELECT]], <2 x i64>* bitcast (i64* getelementptr inbounds ([[STRUCT_COUNTERS]], %struct.Counters* @counters, i64 0, i32 1) to <2 x i64>*), align 8
+; CHECK-NEXT: store <2 x i64> [[SIMPLIFYCFG_MERGE]], <2 x i64>* bitcast (i64* getelementptr inbounds ([[STRUCT_COUNTERS]], %struct.Counters* @counters, i64 0, i32 1) to <2 x i64>*), align 8
; CHECK-NEXT: br label [[TMP10]]
; CHECK: 10:
; CHECK-NEXT: ret i32 0
@@ -128,13 +128,13 @@ define i32 @align_single_zero() local_unnamed_addr {
; CHECK-NEXT: [[AND4:%.*]] = and i64 [[TMP2]], 2
; CHECK-NEXT: [[TOBOOL5:%.*]] = icmp eq i64 [[AND4]], 0
; CHECK-NEXT: [[TMP5:%.*]] = add nsw <2 x i64> [[TMP4]], <i64 1, i64 1>
-; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[TOBOOL5]], <2 x i64> [[TMP4]], <2 x i64> [[TMP5]]
+; CHECK-NEXT: [[SIMPLIFYCFG_MERGE:%.*]] = select i1 [[TOBOOL5]], <2 x i64> [[TMP4]], <2 x i64> [[TMP5]]
; CHECK-NEXT: [[TMP6:%.*]] = xor i1 [[TOBOOL]], true
; CHECK-NEXT: [[TMP7:%.*]] = xor i1 [[TOBOOL5]], true
; CHECK-NEXT: [[TMP8:%.*]] = or i1 [[TMP6]], [[TMP7]]
; CHECK-NEXT: br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP10:%.*]]
; CHECK: 9:
-; CHECK-NEXT: store <2 x i64> [[SPEC_SELECT]], <2 x i64>* bitcast (i64* getelementptr inbounds ([[STRUCT_COUNTERS]], %struct.Counters* @counters, i64 0, i32 1) to <2 x i64>*), align 8
+; CHECK-NEXT: store <2 x i64> [[SIMPLIFYCFG_MERGE]], <2 x i64>* bitcast (i64* getelementptr inbounds ([[STRUCT_COUNTERS]], %struct.Counters* @counters, i64 0, i32 1) to <2 x i64>*), align 8
; CHECK-NEXT: br label [[TMP10]]
; CHECK: 10:
; CHECK-NEXT: ret i32 0
@@ -182,13 +182,13 @@ define i32 @align_single_zero_second_greater_default() local_unnamed_addr {
; CHECK-NEXT: [[AND4:%.*]] = and i64 [[TMP2]], 2
; CHECK-NEXT: [[TOBOOL5:%.*]] = icmp eq i64 [[AND4]], 0
; CHECK-NEXT: [[TMP5:%.*]] = add nsw <2 x i64> [[TMP4]], <i64 1, i64 1>
-; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[TOBOOL5]], <2 x i64> [[TMP4]], <2 x i64> [[TMP5]]
+; CHECK-NEXT: [[SIMPLIFYCFG_MERGE:%.*]] = select i1 [[TOBOOL5]], <2 x i64> [[TMP4]], <2 x i64> [[TMP5]]
; CHECK-NEXT: [[TMP6:%.*]] = xor i1 [[TOBOOL]], true
; CHECK-NEXT: [[TMP7:%.*]] = xor i1 [[TOBOOL5]], true
; CHECK-NEXT: [[TMP8:%.*]] = or i1 [[TMP6]], [[TMP7]]
; CHECK-NEXT: br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP10:%.*]]
; CHECK: 9:
-; CHECK-NEXT: store <2 x i64> [[SPEC_SELECT]], <2 x i64>* bitcast (i64* getelementptr inbounds ([[STRUCT_COUNTERS]], %struct.Counters* @counters, i64 0, i32 1) to <2 x i64>*), align 16
+; CHECK-NEXT: store <2 x i64> [[SIMPLIFYCFG_MERGE]], <2 x i64>* bitcast (i64* getelementptr inbounds ([[STRUCT_COUNTERS]], %struct.Counters* @counters, i64 0, i32 1) to <2 x i64>*), align 16
; CHECK-NEXT: br label [[TMP10]]
; CHECK: 10:
; CHECK-NEXT: ret i32 0
@@ -236,13 +236,13 @@ define i32 @align_both_zero() local_unnamed_addr {
; CHECK-NEXT: [[AND4:%.*]] = and i64 [[TMP2]], 2
; CHECK-NEXT: [[TOBOOL5:%.*]] = icmp eq i64 [[AND4]], 0
; CHECK-NEXT: [[TMP5:%.*]] = add nsw <2 x i64> [[TMP4]], <i64 1, i64 1>
-; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[TOBOOL5]], <2 x i64> [[TMP4]], <2 x i64> [[TMP5]]
+; CHECK-NEXT: [[SIMPLIFYCFG_MERGE:%.*]] = select i1 [[TOBOOL5]], <2 x i64> [[TMP4]], <2 x i64> [[TMP5]]
; CHECK-NEXT: [[TMP6:%.*]] = xor i1 [[TOBOOL]], true
; CHECK-NEXT: [[TMP7:%.*]] = xor i1 [[TOBOOL5]], true
; CHECK-NEXT: [[TMP8:%.*]] = or i1 [[TMP6]], [[TMP7]]
; CHECK-NEXT: br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP10:%.*]]
; CHECK: 9:
-; CHECK-NEXT: store <2 x i64> [[SPEC_SELECT]], <2 x i64>* bitcast (i64* getelementptr inbounds ([[STRUCT_COUNTERS]], %struct.Counters* @counters, i64 0, i32 1) to <2 x i64>*), align 16
+; CHECK-NEXT: store <2 x i64> [[SIMPLIFYCFG_MERGE]], <2 x i64>* bitcast (i64* getelementptr inbounds ([[STRUCT_COUNTERS]], %struct.Counters* @counters, i64 0, i32 1) to <2 x i64>*), align 16
; CHECK-NEXT: br label [[TMP10]]
; CHECK: 10:
; CHECK-NEXT: ret i32 0
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