[llvm] 31cca9e - [VE] Packed v512f32 binop isel and tests
Simon Moll via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 2 01:10:51 PST 2022
Author: Simon Moll
Date: 2022-02-02T10:09:39+01:00
New Revision: 31cca9e6ba99930813fe74e35a723bed770b640f
URL: https://github.com/llvm/llvm-project/commit/31cca9e6ba99930813fe74e35a723bed770b640f
DIFF: https://github.com/llvm/llvm-project/commit/31cca9e6ba99930813fe74e35a723bed770b640f.diff
LOG: [VE] Packed v512f32 binop isel and tests
Reviewed By: kaz7
Differential Revision: https://reviews.llvm.org/D118335
Added:
llvm/test/CodeGen/VE/Packed/vp_fadd.ll
llvm/test/CodeGen/VE/Packed/vp_fmul.ll
llvm/test/CodeGen/VE/Packed/vp_fsub.ll
Modified:
llvm/lib/Target/VE/VVPInstrPatternsVec.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/VE/VVPInstrPatternsVec.td b/llvm/lib/Target/VE/VVPInstrPatternsVec.td
index 74720fd1f4192..bba56fa50e8cb 100644
--- a/llvm/lib/Target/VE/VVPInstrPatternsVec.td
+++ b/llvm/lib/Target/VE/VVPInstrPatternsVec.td
@@ -237,6 +237,13 @@ defm : Binary_rv_vr_vv_ShortLong<vvp_fdiv,
f64, v256f64, "VFDIVD",
f32, v256f32, "VFDIVS">;
+defm : Binary_rv_vv<c_vvp_fadd,
+ i64, v512f32, v512i1, "PVFADD">;
+defm : Binary_rv_vv<c_vvp_fmul,
+ i64, v512f32, v512i1, "PVFMUL">;
+defm : Binary_rv_vv<vvp_fsub,
+ i64, v512f32, v512i1, "PVFSUB">;
+
multiclass Merge_mvv<
SDPatternOperator OpNode,
ValueType DataVT, ValueType MaskVT,
diff --git a/llvm/test/CodeGen/VE/Packed/vp_fadd.ll b/llvm/test/CodeGen/VE/Packed/vp_fadd.ll
new file mode 100644
index 0000000000000..e99c7c47060a8
--- /dev/null
+++ b/llvm/test/CodeGen/VE/Packed/vp_fadd.ll
@@ -0,0 +1,53 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
+
+declare <512 x float> @llvm.vp.fadd.v512f32(<512 x float>, <512 x float>, <512 x i1>, i32)
+
+define fastcc <512 x float> @test_vp_fadd_v512f32_vv(<512 x float> %i0, <512 x float> %i1, <512 x i1> %m, i32 %n) {
+; CHECK-LABEL: test_vp_fadd_v512f32_vv:
+; CHECK: # %bb.0:
+; CHECK-NEXT: adds.w.sx %s0, 1, %s0
+; CHECK-NEXT: and %s0, %s0, (32)0
+; CHECK-NEXT: srl %s0, %s0, 1
+; CHECK-NEXT: lvl %s0
+; CHECK-NEXT: pvfadd %v0, %v0, %v1, %vm2
+; CHECK-NEXT: b.l.t (, %s10)
+ %r0 = call <512 x float> @llvm.vp.fadd.v512f32(<512 x float> %i0, <512 x float> %i1, <512 x i1> %m, i32 %n)
+ ret <512 x float> %r0
+}
+
+define fastcc <512 x float> @test_vp_fadd_v512f32_rv(float %s0, <512 x float> %i1, <512 x i1> %m, i32 %n) {
+; CHECK-LABEL: test_vp_fadd_v512f32_rv:
+; CHECK: # %bb.0:
+; CHECK-NEXT: and %s2, %s0, (32)1
+; CHECK-NEXT: srl %s0, %s0, 32
+; CHECK-NEXT: or %s0, %s0, %s2
+; CHECK-NEXT: adds.w.sx %s1, 1, %s1
+; CHECK-NEXT: and %s1, %s1, (32)0
+; CHECK-NEXT: srl %s1, %s1, 1
+; CHECK-NEXT: lvl %s1
+; CHECK-NEXT: pvfadd %v0, %s0, %v0, %vm2
+; CHECK-NEXT: b.l.t (, %s10)
+ %xins = insertelement <512 x float> undef, float %s0, i32 0
+ %i0 = shufflevector <512 x float> %xins, <512 x float> undef, <512 x i32> zeroinitializer
+ %r0 = call <512 x float> @llvm.vp.fadd.v512f32(<512 x float> %i0, <512 x float> %i1, <512 x i1> %m, i32 %n)
+ ret <512 x float> %r0
+}
+
+define fastcc <512 x float> @test_vp_fadd_v512f32_vr(<512 x float> %i0, float %s1, <512 x i1> %m, i32 %n) {
+; CHECK-LABEL: test_vp_fadd_v512f32_vr:
+; CHECK: # %bb.0:
+; CHECK-NEXT: and %s2, %s0, (32)1
+; CHECK-NEXT: srl %s0, %s0, 32
+; CHECK-NEXT: or %s0, %s0, %s2
+; CHECK-NEXT: adds.w.sx %s1, 1, %s1
+; CHECK-NEXT: and %s1, %s1, (32)0
+; CHECK-NEXT: srl %s1, %s1, 1
+; CHECK-NEXT: lvl %s1
+; CHECK-NEXT: pvfadd %v0, %s0, %v0, %vm2
+; CHECK-NEXT: b.l.t (, %s10)
+ %yins = insertelement <512 x float> undef, float %s1, i32 0
+ %i1 = shufflevector <512 x float> %yins, <512 x float> undef, <512 x i32> zeroinitializer
+ %r0 = call <512 x float> @llvm.vp.fadd.v512f32(<512 x float> %i0, <512 x float> %i1, <512 x i1> %m, i32 %n)
+ ret <512 x float> %r0
+}
diff --git a/llvm/test/CodeGen/VE/Packed/vp_fmul.ll b/llvm/test/CodeGen/VE/Packed/vp_fmul.ll
new file mode 100644
index 0000000000000..6de32a3127c82
--- /dev/null
+++ b/llvm/test/CodeGen/VE/Packed/vp_fmul.ll
@@ -0,0 +1,53 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
+
+declare <512 x float> @llvm.vp.fmul.v512f32(<512 x float>, <512 x float>, <512 x i1>, i32)
+
+define fastcc <512 x float> @test_vp_fmul_v512f32_vv(<512 x float> %i0, <512 x float> %i1, <512 x i1> %m, i32 %n) {
+; CHECK-LABEL: test_vp_fmul_v512f32_vv:
+; CHECK: # %bb.0:
+; CHECK-NEXT: adds.w.sx %s0, 1, %s0
+; CHECK-NEXT: and %s0, %s0, (32)0
+; CHECK-NEXT: srl %s0, %s0, 1
+; CHECK-NEXT: lvl %s0
+; CHECK-NEXT: pvfmul %v0, %v0, %v1, %vm2
+; CHECK-NEXT: b.l.t (, %s10)
+ %r0 = call <512 x float> @llvm.vp.fmul.v512f32(<512 x float> %i0, <512 x float> %i1, <512 x i1> %m, i32 %n)
+ ret <512 x float> %r0
+}
+
+define fastcc <512 x float> @test_vp_fmul_v512f32_rv(float %s0, <512 x float> %i1, <512 x i1> %m, i32 %n) {
+; CHECK-LABEL: test_vp_fmul_v512f32_rv:
+; CHECK: # %bb.0:
+; CHECK-NEXT: and %s2, %s0, (32)1
+; CHECK-NEXT: srl %s0, %s0, 32
+; CHECK-NEXT: or %s0, %s0, %s2
+; CHECK-NEXT: adds.w.sx %s1, 1, %s1
+; CHECK-NEXT: and %s1, %s1, (32)0
+; CHECK-NEXT: srl %s1, %s1, 1
+; CHECK-NEXT: lvl %s1
+; CHECK-NEXT: pvfmul %v0, %s0, %v0, %vm2
+; CHECK-NEXT: b.l.t (, %s10)
+ %xins = insertelement <512 x float> undef, float %s0, i32 0
+ %i0 = shufflevector <512 x float> %xins, <512 x float> undef, <512 x i32> zeroinitializer
+ %r0 = call <512 x float> @llvm.vp.fmul.v512f32(<512 x float> %i0, <512 x float> %i1, <512 x i1> %m, i32 %n)
+ ret <512 x float> %r0
+}
+
+define fastcc <512 x float> @test_vp_fmul_v512f32_vr(<512 x float> %i0, float %s1, <512 x i1> %m, i32 %n) {
+; CHECK-LABEL: test_vp_fmul_v512f32_vr:
+; CHECK: # %bb.0:
+; CHECK-NEXT: and %s2, %s0, (32)1
+; CHECK-NEXT: srl %s0, %s0, 32
+; CHECK-NEXT: or %s0, %s0, %s2
+; CHECK-NEXT: adds.w.sx %s1, 1, %s1
+; CHECK-NEXT: and %s1, %s1, (32)0
+; CHECK-NEXT: srl %s1, %s1, 1
+; CHECK-NEXT: lvl %s1
+; CHECK-NEXT: pvfmul %v0, %s0, %v0, %vm2
+; CHECK-NEXT: b.l.t (, %s10)
+ %yins = insertelement <512 x float> undef, float %s1, i32 0
+ %i1 = shufflevector <512 x float> %yins, <512 x float> undef, <512 x i32> zeroinitializer
+ %r0 = call <512 x float> @llvm.vp.fmul.v512f32(<512 x float> %i0, <512 x float> %i1, <512 x i1> %m, i32 %n)
+ ret <512 x float> %r0
+}
diff --git a/llvm/test/CodeGen/VE/Packed/vp_fsub.ll b/llvm/test/CodeGen/VE/Packed/vp_fsub.ll
new file mode 100644
index 0000000000000..8c2e19c68543b
--- /dev/null
+++ b/llvm/test/CodeGen/VE/Packed/vp_fsub.ll
@@ -0,0 +1,56 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
+
+declare <512 x float> @llvm.vp.fsub.v512f32(<512 x float>, <512 x float>, <512 x i1>, i32)
+
+define fastcc <512 x float> @test_vp_fsub_v512f32_vv(<512 x float> %i0, <512 x float> %i1, <512 x i1> %m, i32 %n) {
+; CHECK-LABEL: test_vp_fsub_v512f32_vv:
+; CHECK: # %bb.0:
+; CHECK-NEXT: adds.w.sx %s0, 1, %s0
+; CHECK-NEXT: and %s0, %s0, (32)0
+; CHECK-NEXT: srl %s0, %s0, 1
+; CHECK-NEXT: lvl %s0
+; CHECK-NEXT: pvfsub %v0, %v0, %v1, %vm2
+; CHECK-NEXT: b.l.t (, %s10)
+ %r0 = call <512 x float> @llvm.vp.fsub.v512f32(<512 x float> %i0, <512 x float> %i1, <512 x i1> %m, i32 %n)
+ ret <512 x float> %r0
+}
+
+define fastcc <512 x float> @test_vp_fsub_v512f32_rv(float %s0, <512 x float> %i1, <512 x i1> %m, i32 %n) {
+; CHECK-LABEL: test_vp_fsub_v512f32_rv:
+; CHECK: # %bb.0:
+; CHECK-NEXT: and %s2, %s0, (32)1
+; CHECK-NEXT: srl %s0, %s0, 32
+; CHECK-NEXT: or %s0, %s0, %s2
+; CHECK-NEXT: adds.w.sx %s1, 1, %s1
+; CHECK-NEXT: and %s1, %s1, (32)0
+; CHECK-NEXT: srl %s1, %s1, 1
+; CHECK-NEXT: lvl %s1
+; CHECK-NEXT: pvfsub %v0, %s0, %v0, %vm2
+; CHECK-NEXT: b.l.t (, %s10)
+ %xins = insertelement <512 x float> undef, float %s0, i32 0
+ %i0 = shufflevector <512 x float> %xins, <512 x float> undef, <512 x i32> zeroinitializer
+ %r0 = call <512 x float> @llvm.vp.fsub.v512f32(<512 x float> %i0, <512 x float> %i1, <512 x i1> %m, i32 %n)
+ ret <512 x float> %r0
+}
+
+define fastcc <512 x float> @test_vp_fsub_v512f32_vr(<512 x float> %i0, float %s1, <512 x i1> %m, i32 %n) {
+; CHECK-LABEL: test_vp_fsub_v512f32_vr:
+; CHECK: # %bb.0:
+; CHECK-NEXT: and %s2, %s0, (32)1
+; CHECK-NEXT: srl %s0, %s0, 32
+; CHECK-NEXT: or %s0, %s0, %s2
+; CHECK-NEXT: lea %s2, 256
+; CHECK-NEXT: lvl %s2
+; CHECK-NEXT: vbrd %v1, %s0
+; CHECK-NEXT: adds.w.sx %s0, 1, %s1
+; CHECK-NEXT: and %s0, %s0, (32)0
+; CHECK-NEXT: srl %s0, %s0, 1
+; CHECK-NEXT: lvl %s0
+; CHECK-NEXT: pvfsub %v0, %v0, %v1, %vm2
+; CHECK-NEXT: b.l.t (, %s10)
+ %yins = insertelement <512 x float> undef, float %s1, i32 0
+ %i1 = shufflevector <512 x float> %yins, <512 x float> undef, <512 x i32> zeroinitializer
+ %r0 = call <512 x float> @llvm.vp.fsub.v512f32(<512 x float> %i0, <512 x float> %i1, <512 x i1> %m, i32 %n)
+ ret <512 x float> %r0
+}
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