[PATCH] D117955: [TableGen][RISCV] Relax a restriction in generating patterns for commutable SDNodes.

[Craig Topper via Phabricator via llvm-commits]

craig.topper updated this revision to Diff 405005.
craig.topper added a comment.

Simplify code as suggested.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117955/new/

https://reviews.llvm.org/D117955

Files:
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vand-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vor-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll
  llvm/utils/TableGen/CodeGenDAGPatterns.cpp

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