[PATCH] D110579: [AMDGPU] Add a new intrinsic to control fp_trunc rounding mode

[Julien Pagès via Phabricator via llvm-commits]

jpages marked 2 inline comments as done.
jpages added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp:3252
     return selectG_SBFX_UBFX(I);
+  case AMDGPU::G_FPTRUNC_ROUND_UPWARD:
+  case AMDGPU::G_FPTRUNC_ROUND_DOWNWARD: {
----------------
foad wrote:
> jpages wrote:
> > foad wrote:
> > > Can this be done with patterns in the tablegen files instead of C++ code?
> > Maybe it's possible, but I could not find a way to match both the G_FPTRUNC_ROUND_UPWARD and the selection DAG version. 
> > 
> > So I let this one in C++.
> You can get some clues about GlobalISel pattern problems by running tablegen with -warn-on-skipped-patterns like this:
> ```
> $ llvm-tblgen -gen-global-isel -I lib/Target/AMDGPU -I build/include -I include -I lib/Target lib/Target/AMDGPU/AMDGPUGISel.td -warn-on-skipped-patterns
> ...
> lib/Target/AMDGPU/SIInstructions.td:186:1: warning: Skipped pattern: Pattern operator lacks an equivalent Instruction (AMDGPUISD::FPTRUNC_ROUND_UPWARD)
> def FPTRUNC_UPWARD_PSEUDO : VPseudoInstSI <(outs VGPR_32:$vdst),
> ^
> ...
> lib/Target/AMDGPU/SIInstructions.td:190:1: warning: Skipped pattern: Pattern operator lacks an equivalent Instruction (AMDGPUISD::FPTRUNC_ROUND_DOWNWARD)
> def FPTRUNC_DOWNWARD_PSEUDO : VPseudoInstSI <(outs VGPR_32:$vdst),
> ^
> ```
> This means you need to add some `GINodeEquiv` lines in AMDGPUGISel.td.
Thanks again, I didn't know about this command


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https://reviews.llvm.org/D110579