[PATCH] D118595: [AARCH64][DAGCombine] Add combine for negation of CSEL absolute value pattern.

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

Hello. This sounds good. It is similar to the patch in D112204 <https://reviews.llvm.org/D112204> (but I din't have any time to continue that, glad to see you looking into the same thing!)

Feel free to steal what is useful from it, if you thing the suggested simplification is a good idea.



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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:14699
 
+// Try to fold (sub Y, (csel X, -X, pl)) -> (add Y, (csel -X, X, pl)) when
+// condition came from (subs X, 0). This matches the CSEL expansion of
----------------
I think we might be able to generalize this a bit, possibly simplifying it in the process. If we have `neg (csel x, y, cc)`, we can convert to `csel (neg x), (neg y), cc`, and providing at least one of x and y simplify it will be the same cost or cheaper (with a csneg operation).

I think that means that the condition is unimportant, and we won't need to emit the Add. It won't handle all the same patterns this does, both might be quite rare for cases that are not -abs (as llvm will have often optimized before this point already), but might be more straight forward.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:17671
   case ISD::SUB:
+    if (SDValue Val = performCombineSubABS(N, DAG)) {
+      return Val;
----------------
I think you can include this in performAddSubCombine, just with a check that the opcode is ISD::SUB in there or performCombineSubABS.


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https://reviews.llvm.org/D118595