[PATCH] D118681: [AArch64] Do not use ABI alignment for mops.memset.tag

[Nikita Popov via Phabricator via llvm-commits]

nikic updated this revision to Diff 404867.
nikic added a comment.

Add test with align attribute. I don't think this has any actual effect, at least I don't see how the lowering would depend on alignment.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D118681/new/

https://reviews.llvm.org/D118681

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/aarch64-mops-mte.ll


Index: llvm/test/CodeGen/AArch64/aarch64-mops-mte.ll
===================================================================
--- llvm/test/CodeGen/AArch64/aarch64-mops-mte.ll
+++ llvm/test/CodeGen/AArch64/aarch64-mops-mte.ll
@@ -324,3 +324,34 @@
   %r = tail call i8* @llvm.aarch64.mops.memset.tag(i8* %dst, i8 %value_trunc, i64 %size)
   ret i8* %r
 }
+
+define i8* @memset_tagged_size_aligned(i8* %dst, i64 %size, i32 %value) {
+; GISel-O0-LABEL: memset_tagged_size_aligned:
+; GISel-O0:       // %bb.0: // %entry
+; GISel-O0-NEXT:    // implicit-def: $x8
+; GISel-O0-NEXT:    mov w8, w2
+; GISel-O0-NEXT:    setgp [x0]!, x1!, x8
+; GISel-O0-NEXT:    setgm [x0]!, x1!, x8
+; GISel-O0-NEXT:    setge [x0]!, x1!, x8
+; GISel-O0-NEXT:    ret
+;
+; GISel-LABEL: memset_tagged_size_aligned:
+; GISel:       // %bb.0: // %entry
+; GISel-NEXT:    // kill: def $w2 killed $w2 def $x2
+; GISel-NEXT:    setgp [x0]!, x1!, x2
+; GISel-NEXT:    setgm [x0]!, x1!, x2
+; GISel-NEXT:    setge [x0]!, x1!, x2
+; GISel-NEXT:    ret
+;
+; SDAG-LABEL: memset_tagged_size_aligned:
+; SDAG:       // %bb.0: // %entry
+; SDAG-NEXT:    // kill: def $w2 killed $w2 def $x2
+; SDAG-NEXT:    setgp [x0]!, x1!, x2
+; SDAG-NEXT:    setgm [x0]!, x1!, x2
+; SDAG-NEXT:    setge [x0]!, x1!, x2
+; SDAG-NEXT:    ret
+entry:
+  %value_trunc = trunc i32 %value to i8
+  %r = tail call i8* @llvm.aarch64.mops.memset.tag(i8* align 16 %dst, i8 %value_trunc, i64 %size)
+  ret i8* %r
+}
Index: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -11928,12 +11928,11 @@
   case Intrinsic::aarch64_mops_memset_tag: {
     Value *Dst = I.getArgOperand(0);
     Value *Val = I.getArgOperand(1);
-    PointerType *PtrTy = cast<PointerType>(Dst->getType());
     Info.opc = ISD::INTRINSIC_W_CHAIN;
     Info.memVT = MVT::getVT(Val->getType());
     Info.ptrVal = Dst;
     Info.offset = 0;
-    Info.align = DL.getABITypeAlign(PtrTy->getPointerElementType());
+    Info.align = I.getParamAlign(0).valueOrOne();
     Info.flags = MachineMemOperand::MOStore;
     // The size of the memory being operated on is unknown at this point
     Info.size = MemoryLocation::UnknownSize;


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