[PATCH] D118419: [AMDGPU] Allow scalar loads after barrier

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec updated this revision to Diff 404701.
rampitec added a comment.

Further study showed that a barrier or fence not only defines the load of interest but also clobbering any other load dominating them (for the same reason). The change adds aliasing disambiguation while walking up the tree to only consider defs affecting original memory location.

- Use getClobberingMemoryAccess() in the loop with the memory location of the original load to skip any store which may not alias.
- Added more tests and generated opt metadata checks as well.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D118419/new/

https://reviews.llvm.org/D118419

Files:
  llvm/lib/Target/AMDGPU/AMDGPUAnnotateUniformValues.cpp
  llvm/test/CodeGen/AMDGPU/noclobber-barrier.ll

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