[PATCH] D118582: [RISCV] Update the computeKnownBitsForTargetNode for RISCVISD::READ_VLENB to consider Zve/Zvl.
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Jan 31 09:13:50 PST 2022
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG09606d6a635b: [RISCV] Update the computeKnownBitsForTargetNode for RISCVISD::READ_VLENB to… (authored by craig.topper).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D118582/new/
https://reviews.llvm.org/D118582
Files:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVSubtarget.h
Index: llvm/lib/Target/RISCV/RISCVSubtarget.h
===================================================================
--- llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -195,6 +195,7 @@
return 0;
}
+ unsigned getMinVLen() const { return ZvlLen; }
RISCVABI::ABI getTargetABI() const { return TargetABI; }
bool isRegisterReservedByUser(Register i) const {
assert(i < RISCV::NUM_TARGET_REGS && "Register out of range");
Index: llvm/lib/Target/RISCV/RISCVISelLowering.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -8274,12 +8274,17 @@
}
break;
}
- case RISCVISD::READ_VLENB:
- // We assume VLENB is at least 16 bytes.
- Known.Zero.setLowBits(4);
+ case RISCVISD::READ_VLENB: {
+ // If we know the minimum VLen from Zvl extensions, we can use that to
+ // determine the trailing zeros of VLENB.
+ // FIXME: Limit to 128 bit vectors until we have more testing.
+ unsigned MinVLenB = std::min(128U, Subtarget.getMinVLen()) / 8;
+ if (MinVLenB > 0)
+ Known.Zero.setLowBits(Log2_32(MinVLenB));
// We assume VLENB is no more than 65536 / 8 bytes.
Known.Zero.setBitsFrom(14);
break;
+ }
case ISD::INTRINSIC_W_CHAIN:
case ISD::INTRINSIC_WO_CHAIN: {
unsigned IntNo =
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