[llvm] 2e45e8a - [RISCV] Add a fatal error if ISD::VSCALE is used with Zvl32b.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Mon Jan 31 09:13:38 PST 2022
Author: Craig Topper
Date: 2022-01-31T09:13:14-08:00
New Revision: 2e45e8abb11b007ec9f575b1ea9b20b42fa74445
URL: https://github.com/llvm/llvm-project/commit/2e45e8abb11b007ec9f575b1ea9b20b42fa74445
DIFF: https://github.com/llvm/llvm-project/commit/2e45e8abb11b007ec9f575b1ea9b20b42fa74445.diff
LOG: [RISCV] Add a fatal error if ISD::VSCALE is used with Zvl32b.
We convert VLEN to vscale by dividing by RVVBitsPerBlock which is
currently 64. This is only correct if VLEN is evenly divisible by
64. With only Zvl32b we can't assume that.
This patch adds a fatal_error to prevent generating code that may
be broken.
We probably need to look at how we size stack frame objects too.
Reviewed By: frasercrmck
Differential Revision: https://reviews.llvm.org/D118583
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index de240583f949..72bae0679d50 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -3076,6 +3076,8 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
// minimum size. e.g. <vscale x 2 x i32>. VLENB is in bytes so we calculate
// vscale as VLENB / 8.
static_assert(RISCV::RVVBitsPerBlock == 64, "Unexpected bits per block!");
+ if (Subtarget.getMinVLen() < RISCV::RVVBitsPerBlock)
+ report_fatal_error("Support for VLEN==32 is incomplete.");
if (isa<ConstantSDNode>(Op.getOperand(0))) {
// We assume VLENB is a multiple of 8. We manually choose the best shift
// here because SimplifyDemandedBits isn't always able to simplify it.
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