[PATCH] D117871: [AArch64][CodeGen] Always use SVE (when enabled) to lower integer divides

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen added inline comments.


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Comment at: llvm/test/CodeGen/AArch64/sve-fixed-length-int-div.ll:1
-; RUN: llc -aarch64-sve-vector-bits-min=128  -asm-verbose=0 < %s | FileCheck %s -check-prefix=NO_SVE
 ; RUN: llc -aarch64-sve-vector-bits-min=256  -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_EQ_256
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Instead of duplicating these tests and moving these check lines to a different file, I'd rather have a RUN line with a check-prefix=VBITS_EQ_128, where you only add check lines for the cases where it currently already has CHECK and CHECK-NEXT lines.

For all places where the expected CHECK lines are different from the expected output for VBITS_EQ_128, please add a `FIXME: The code should be equivalent. Remove CHECK lines in favour of VBITS_EQ_128`. or something like that. When we fix the issue that having a larger vector width generates different code for the same fixed-width vectors, it will be obvious which lines to remove, and we don't end up with a stale test file (e.g. sve-fixed-length-int-div-128.ll)


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117871/new/

https://reviews.llvm.org/D117871