[PATCH] D118394: [AArch64][NEON][SVE] Lower FCOPYSIGN using AArch64ISD::BSP

Mon Jan 31 06:51:24 PST 2022

DavidTruby added a comment.

Apologies to reviewers for the confusion above, I believe this patch should now be correct in all the given cases.

I also fear the intent here may be a bit vague so I should clarify: what I'm trying to do is unify the lowering of FCOPYSIGN for scalar, NEON, SVE and SVE2 cases by lowering it to the AArch64ISD::BSP pseudo-instruction, which should have correct lowering for each architecture. 
There didn't as yet exist SVE or SVE2 lowering for BSP, so that is added here as well.
As such, there should be no change to the code generation for SVE or NEON, other than possibly a few instruction orders changing. For SVE2 we should use the bsl instruction there that SVE does not have.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D118394/new/

https://reviews.llvm.org/D118394