[llvm] ffd0e46 - [X86] Add mul(x,x) tests showing miscompile

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2022-01-31T11:07:03Z
New Revision: ffd0e464b4b98ffa9a511b09dd36cfba33fed8a1

URL: https://github.com/llvm/llvm-project/commit/ffd0e464b4b98ffa9a511b09dd36cfba33fed8a1
DIFF: https://github.com/llvm/llvm-project/commit/ffd0e464b4b98ffa9a511b09dd36cfba33fed8a1.diff

LOG: [X86] Add mul(x,x) tests showing miscompile

As raised by @efriedma on D117995 - the source must not be undef/poison to demand any bits in mul(x,x) other than bit[1]

https://alive2.llvm.org/ce/z/Cxkjen

Added: 
    

Modified: 
    llvm/test/CodeGen/X86/combine-mul.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/X86/combine-mul.ll b/llvm/test/CodeGen/X86/combine-mul.ll
index 4370b22c5aae6..57d85e1c1c9ed 100644
--- a/llvm/test/CodeGen/X86/combine-mul.ll
+++ b/llvm/test/CodeGen/X86/combine-mul.ll
@@ -393,6 +393,41 @@ define <4 x i32> @combine_mul_self_knownbits_vector(<4 x i32> %x) {
   ret <4 x i32> %2
 }
 
+; mul(x,x) - bit[1] is 0, but if demanding the other bits the source must not be undef/poison
+
+define i64 @combine_mul_self_demandedbits(i64 %x) {
+; SSE-LABEL: combine_mul_self_demandedbits:
+; SSE:       # %bb.0:
+; SSE-NEXT:    movq %rdi, %rax
+; SSE-NEXT:    imulq %rdi, %rax
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: combine_mul_self_demandedbits:
+; AVX:       # %bb.0:
+; AVX-NEXT:    movq %rdi, %rax
+; AVX-NEXT:    imulq %rdi, %rax
+; AVX-NEXT:    retq
+  %1 = mul i64 %x, %x
+  %2 = and i64 %1, -3
+  ret i64 %2
+}
+
+define <4 x i32> @combine_mul_self_demandedbits_vector(<4 x i32> %x) {
+; SSE-LABEL: combine_mul_self_demandedbits_vector:
+; SSE:       # %bb.0:
+; SSE-NEXT:    pmulld %xmm0, %xmm0
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: combine_mul_self_demandedbits_vector:
+; AVX:       # %bb.0:
+; AVX-NEXT:    vpmulld %xmm0, %xmm0, %xmm0
+; AVX-NEXT:    retq
+  %1 = freeze <4 x i32> %x
+  %2 = mul <4 x i32> %1, %1
+  %3 = and <4 x i32> %2, <i32 -3, i32 -3, i32 -3, i32 -3>
+  ret <4 x i32> %3
+}
+
 ; This would infinite loop because DAGCombiner wants to turn this into a shift,
 ; but x86 lowering wants to avoid non-uniform vector shift amounts.