[PATCH] D118584: [AArch64] Combine ISD::AND into AArch64ISD::ANDS

[David Sherwood via Phabricator via llvm-commits]

david-arm added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:14084
+// cases.
+static SDValue performANDSCombine(SDNode *N, unsigned GenericOpc,
+                                  TargetLowering::DAGCombinerInfo &DCI) {
----------------
Is there any need to pass in `GenericOpc` as it seems to always be ISD::AND?


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:14094
+    SDValue Res = DCI.DAG.getNode(GenericOpc, DL, VT, LHS, RHS);
+    return DCI.DAG.getMergeValues({Res, DCI.DAG.getConstant(0, DL, MVT::i32)},
+                                  DL);
----------------
Do you have to do this given we're not merging any results together? For example, does it work if you just do

  return DCI.DAG.getNode(GenericOpc, DL, VT, LHS, RHS);

?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D118584/new/

https://reviews.llvm.org/D118584