[PATCH] D118419: [AMDGPU] Allow scalar loads after barrier
Stanislav Mekhanoshin via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 27 16:39:25 PST 2022
rampitec created this revision.
rampitec added reviewers: arsenm, vpykhtin.
Herald added subscribers: foad, kerbowa, asbirlea, george.burgess.iv, hiraditya, t-tye, tpr, dstuttard, yaxunl, nhaehnle, jvesely, kzhuravl.
rampitec requested review of this revision.
Herald added a subscriber: wdng.
Herald added a project: LLVM.
Currently we cannot convert a vector load into scalar if there
is dominating barrier or fence. It is considered a clobbering
memory access to prevent memory operations reordering. While
reordering is not possible the actual memory is not being clobbered
by a barrier or fence and we can still use a scalar load for a
uniform pointer.
The solution is not to bail on a first clobbering access but
traverse MemorySSA to the root excluding barriers and fences.
https://reviews.llvm.org/D118419
Files:
llvm/lib/Target/AMDGPU/AMDGPUAnnotateUniformValues.cpp
llvm/test/CodeGen/AMDGPU/noclobber-barrier.ll
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D118419.403835.patch
Type: text/x-patch
Size: 7841 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20220128/b6dcf20c/attachment-0001.bin>
More information about the llvm-commits
mailing list