[PATCH] D118415: AMDGPU: Reserve v32 if we may need to copy between AGPRs on gfx908

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added a comment.

I think it has to be dynamic depending on the requested occupancy. But even then it can drop the occupancy of a kernel if it uses less than 32 registers, which not uncommon. I do not believe we can reserve it that high.



================
Comment at: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp:601
+  } else {
+    Tmp = RS.scavengeRegister(&AMDGPU::VGPR_32RegClass, 0);
   }
----------------
It misses error reporting and setRegUsed call.


================
Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp:607
+  // available at all times.
+  if (ST.hasMAIInsts() && !ST.hasGFX90AInsts())
+    reserveRegisterTuples(Reserved, AMDGPU::VGPR32);
----------------
You can skip it if !MFI->usesAGPRs(MF).


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https://reviews.llvm.org/D118415