[PATCH] D118308: AMDGPU: Handle addrspacecast of constant 32-bit to flat

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added reviewers: mareko, nhaehnle, sebastian-ne, foad, AMDGPU.
Herald added subscribers: kerbowa, hiraditya, t-tye, tpr, dstuttard, yaxunl, jvesely, kzhuravl.
arsenm requested review of this revision.
Herald added a subscriber: wdng.
Herald added a project: LLVM.

I accidentally made this work on the GlobalISel path, and there's no
real reason not to handle this.


https://reviews.llvm.org/D118308

Files:
  llvm/lib/Target/AMDGPU/SIISelLowering.cpp
  llvm/test/CodeGen/AMDGPU/addrspacecast.ll
  llvm/test/CodeGen/AMDGPU/invalid-addrspacecast.ll


Index: llvm/test/CodeGen/AMDGPU/invalid-addrspacecast.ll
===================================================================
--- llvm/test/CodeGen/AMDGPU/invalid-addrspacecast.ll
+++ llvm/test/CodeGen/AMDGPU/invalid-addrspacecast.ll
@@ -7,13 +7,6 @@
   ret void
 }
 
-; ERROR: error: <unknown>:0:0: in function use_constant32bit_to_flat_addrspacecast void (i32 addrspace(6)*): invalid addrspacecast
-define amdgpu_kernel void @use_constant32bit_to_flat_addrspacecast(i32 addrspace(6)* %ptr) #0 {
-  %stof = addrspacecast i32 addrspace(6)* %ptr to i32*
-  store volatile i32 7, i32* %stof
-  ret void
-}
-
 ; ERROR: error: <unknown>:0:0: in function use_local_to_constant32bit_addrspacecast void (i32 addrspace(3)*): invalid addrspacecast
 define amdgpu_kernel void @use_local_to_constant32bit_addrspacecast(i32 addrspace(3)* %ptr) #0 {
   %stof = addrspacecast i32 addrspace(3)* %ptr to i32 addrspace(6)*
Index: llvm/test/CodeGen/AMDGPU/addrspacecast.ll
===================================================================
--- llvm/test/CodeGen/AMDGPU/addrspacecast.ll
+++ llvm/test/CodeGen/AMDGPU/addrspacecast.ll
@@ -405,9 +405,32 @@
   ret void
 }
 
+; GCN-LABEL: {{^}}use_constant32bit_to_flat_addrspacecast_0:
+; GCN: s_load_dword [[PTR:s[0-9]+]],
+; GCN: v_mov_b32_e32 v[[HI:[0-9]+]], 0
+; GCN: v_mov_b32_e32 v[[LO:[0-9]+]], [[PTR]]
+; GCN: flat_load_dword v{{[0-9]+}}, v{{\[}}[[LO]]:[[HI]]{{\]}}
+define amdgpu_kernel void @use_constant32bit_to_flat_addrspacecast_0(i32 addrspace(6)* %ptr) #0 {
+  %stof = addrspacecast i32 addrspace(6)* %ptr to i32*
+  %load = load volatile i32, i32* %stof
+  ret void
+}
+
+; GCN-LABEL: {{^}}use_constant32bit_to_flat_addrspacecast_1:
+; GCN: s_load_dword [[PTR:s[0-9]+]],
+; GCN: v_mov_b32_e32 v[[HI:[0-9]+]], 0xffff8000
+; GCN: v_mov_b32_e32 v[[LO:[0-9]+]], [[PTR]]
+; GCN: flat_load_dword v{{[0-9]+}}, v{{\[}}[[LO]]:[[HI]]{{\]}}
+define amdgpu_kernel void @use_constant32bit_to_flat_addrspacecast_1(i32 addrspace(6)* %ptr) #3 {
+  %stof = addrspacecast i32 addrspace(6)* %ptr to i32*
+  %load = load volatile i32, i32* %stof
+  ret void
+}
+
 declare void @llvm.amdgcn.s.barrier() #1
 declare i32 @llvm.amdgcn.workitem.id.x() #2
 
 attributes #0 = { nounwind }
 attributes #1 = { nounwind convergent }
 attributes #2 = { nounwind readnone }
+attributes #3 = { nounwind "amdgpu-32bit-address-high-bits"="0xffff8000" }
Index: llvm/lib/Target/AMDGPU/SIISelLowering.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -5632,6 +5632,15 @@
     }
   }
 
+  if (SrcAS == AMDGPUAS::CONSTANT_ADDRESS_32BIT &&
+      Op.getValueType() == MVT::i64) {
+    const SIMachineFunctionInfo *Info =
+        DAG.getMachineFunction().getInfo<SIMachineFunctionInfo>();
+    SDValue Hi = DAG.getConstant(Info->get32BitAddressHighBits(), SL, MVT::i32);
+    SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32, Src, Hi);
+    return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Vec);
+  }
+
   if (ASC->getDestAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS_32BIT &&
       Src.getValueType() == MVT::i64)
     return DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, Src);


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