[llvm] e107518 - [RISCV] Custom lower brev8 intrinsic to RISCVISD::GREV.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2022-01-30T12:41:09-08:00
New Revision: e1075186a6458de75492f5de5fb8b8139097ff5f

URL: https://github.com/llvm/llvm-project/commit/e1075186a6458de75492f5de5fb8b8139097ff5f
DIFF: https://github.com/llvm/llvm-project/commit/e1075186a6458de75492f5de5fb8b8139097ff5f.diff

LOG: [RISCV] Custom lower brev8 intrinsic to RISCVISD::GREV.

We can use the RISCVISD::GREV encoding that swaps the bits in
each byte.  This allows it to use the existing computeKnownBits
support for RISCVISD::GREV.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
    llvm/test/CodeGen/RISCV/rv32zbkb-intrinsic.ll
    llvm/test/CodeGen/RISCV/rv64zbkb-intrinsic.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 54b909ec94e0e..838e2bbeb96fc 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -4465,9 +4465,13 @@ SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
     return DAG.getRegister(RISCV::X4, PtrVT);
   }
   case Intrinsic::riscv_orc_b:
-    // Lower to the GORCI encoding for orc.b.
-    return DAG.getNode(RISCVISD::GORC, DL, XLenVT, Op.getOperand(1),
+  case Intrinsic::riscv_brev8: {
+    // Lower to the GORCI encoding for orc.b or the GREVI encoding for brev8.
+    unsigned Opc =
+        IntNo == Intrinsic::riscv_brev8 ? RISCVISD::GREV : RISCVISD::GORC;
+    return DAG.getNode(Opc, DL, XLenVT, Op.getOperand(1),
                        DAG.getConstant(7, DL, XLenVT));
+  }
   case Intrinsic::riscv_grev:
   case Intrinsic::riscv_gorc: {
     unsigned Opc =

diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
index c60f31ae1d6b3..50849949bfb48 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
@@ -1172,10 +1172,6 @@ def : PatGprGpr<riscv_bfp, BFP>;
 let Predicates = [HasStdExtZbf, IsRV64] in
 def : PatGprGpr<riscv_bfpw, BFPW>;
 
-let Predicates = [HasStdExtZbkb] in {
-def : PatGpr<int_riscv_brev8, BREV8>;
-} // Predicates = [HasStdExtZbkb]
-
 let Predicates = [HasStdExtZbkb, IsRV32] in {
 def : PatGpr<int_riscv_zip, ZIP_RV32>;
 def : PatGpr<int_riscv_unzip, UNZIP_RV32>;

diff  --git a/llvm/test/CodeGen/RISCV/rv32zbkb-intrinsic.ll b/llvm/test/CodeGen/RISCV/rv32zbkb-intrinsic.ll
index 9efd7e5feb3f0..a4d76f8e82103 100644
--- a/llvm/test/CodeGen/RISCV/rv32zbkb-intrinsic.ll
+++ b/llvm/test/CodeGen/RISCV/rv32zbkb-intrinsic.ll
@@ -13,6 +13,18 @@ define i32 @brev8(i32 %a) nounwind {
   ret i32 %val
 }
 
+; Test that rev8 is recognized as preserving zero extension.
+define zeroext i16 @brev8_knownbits(i16 zeroext %a) nounwind {
+; RV32ZBKB-LABEL: brev8_knownbits:
+; RV32ZBKB:       # %bb.0:
+; RV32ZBKB-NEXT:    brev8 a0, a0
+; RV32ZBKB-NEXT:    ret
+  %zext = zext i16 %a to i32
+  %val = call i32 @llvm.riscv.brev8(i32 %zext)
+  %trunc = trunc i32 %val to i16
+  ret i16 %trunc
+}
+
 declare i32 @llvm.bswap.i32(i32)
 
 define i32 @rev8_i32(i32 %a) nounwind {

diff  --git a/llvm/test/CodeGen/RISCV/rv64zbkb-intrinsic.ll b/llvm/test/CodeGen/RISCV/rv64zbkb-intrinsic.ll
index ec3196beacd0e..d3ba14c71cb92 100644
--- a/llvm/test/CodeGen/RISCV/rv64zbkb-intrinsic.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zbkb-intrinsic.ll
@@ -13,6 +13,18 @@ define i64 @brev8(i64 %a) nounwind {
   ret i64 %val
 }
 
+; Test that rev8 is recognized as preserving zero extension.
+define zeroext i16 @brev8_knownbits(i16 zeroext %a) nounwind {
+; RV64ZBKB-LABEL: brev8_knownbits:
+; RV64ZBKB:       # %bb.0:
+; RV64ZBKB-NEXT:    brev8 a0, a0
+; RV64ZBKB-NEXT:    ret
+  %zext = zext i16 %a to i64
+  %val = call i64 @llvm.riscv.brev8(i64 %zext)
+  %trunc = trunc i64 %val to i16
+  ret i16 %trunc
+}
+
 declare i64 @llvm.bswap.i64(i64)
 
 define i64 @rev8_i64(i64 %a) {