[llvm] 2bea207 - [CodeGen] Use default member initialization (NFC)
Kazu Hirata via llvm-commits
llvm-commits at lists.llvm.org
Sun Jan 30 12:33:12 PST 2022
Author: Kazu Hirata
Date: 2022-01-30T12:32:51-08:00
New Revision: 2bea207d266534a34cb9587bfbebef7e0662f0d6
URL: https://github.com/llvm/llvm-project/commit/2bea207d266534a34cb9587bfbebef7e0662f0d6
DIFF: https://github.com/llvm/llvm-project/commit/2bea207d266534a34cb9587bfbebef7e0662f0d6.diff
LOG: [CodeGen] Use default member initialization (NFC)
Identified with modernize-use-default-member-init.
Added:
Modified:
llvm/include/llvm/CodeGen/DIE.h
llvm/include/llvm/CodeGen/FastISel.h
llvm/include/llvm/CodeGen/GlobalISel/LegacyLegalizerInfo.h
llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
llvm/include/llvm/CodeGen/IntrinsicLowering.h
llvm/include/llvm/CodeGen/MachineFrameInfo.h
llvm/include/llvm/CodeGen/MachineModuleSlotTracker.h
llvm/include/llvm/CodeGen/MachineOperand.h
llvm/include/llvm/CodeGen/MachineRegisterInfo.h
llvm/include/llvm/CodeGen/SelectionDAGISel.h
llvm/include/llvm/CodeGen/SlotIndexes.h
llvm/include/llvm/CodeGen/SwitchLoweringUtils.h
llvm/include/llvm/CodeGen/TargetCallingConv.h
llvm/include/llvm/CodeGen/VirtRegMap.h
llvm/lib/CodeGen/AsmPrinter/DIE.cpp
llvm/lib/CodeGen/AsmPrinter/DwarfCFIException.cpp
llvm/lib/CodeGen/AsmPrinter/DwarfException.h
llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
llvm/lib/CodeGen/AsmPrinter/DwarfUnit.h
llvm/lib/CodeGen/CodeGenPrepare.cpp
llvm/lib/CodeGen/EarlyIfConversion.cpp
llvm/lib/CodeGen/ExpandMemCmp.cpp
llvm/lib/CodeGen/GlobalISel/LegacyLegalizerInfo.cpp
llvm/lib/CodeGen/IfConversion.cpp
llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp
llvm/lib/CodeGen/LiveDebugValues/VarLocBasedImpl.cpp
llvm/lib/CodeGen/MachineModuleSlotTracker.cpp
llvm/lib/CodeGen/MachineRegisterInfo.cpp
llvm/lib/CodeGen/PostRASchedulerList.cpp
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
llvm/lib/CodeGen/SlotIndexes.cpp
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/DIE.h b/llvm/include/llvm/CodeGen/DIE.h
index 32df448b91a11..7f7372630dbec 100644
--- a/llvm/include/llvm/CodeGen/DIE.h
+++ b/llvm/include/llvm/CodeGen/DIE.h
@@ -886,8 +886,8 @@ class DIEUnit {
DIE Die;
/// The section this unit will be emitted in. This may or may not be set to
/// a valid section depending on the client that is emitting DWARF.
- MCSection *Section;
- uint64_t Offset; /// .debug_info or .debug_types absolute section offset.
+ MCSection *Section = nullptr;
+ uint64_t Offset = 0; /// .debug_info or .debug_types absolute section offset.
protected:
virtual ~DIEUnit() = default;
diff --git a/llvm/include/llvm/CodeGen/FastISel.h b/llvm/include/llvm/CodeGen/FastISel.h
index 9c7e688da6a7a..775698a66adae 100644
--- a/llvm/include/llvm/CodeGen/FastISel.h
+++ b/llvm/include/llvm/CodeGen/FastISel.h
@@ -217,12 +217,12 @@ class FastISel {
/// for use in the current block. It resets to EmitStartPt when it makes sense
/// (for example, it's usually profitable to avoid function calls between the
/// definition and the use)
- MachineInstr *LastLocalValue;
+ MachineInstr *LastLocalValue = nullptr;
/// The top most instruction in the current block that is allowed for
/// emitting local variables. LastLocalValue resets to EmitStartPt when it
/// makes sense (for example, on function calls)
- MachineInstr *EmitStartPt;
+ MachineInstr *EmitStartPt = nullptr;
public:
virtual ~FastISel();
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/LegacyLegalizerInfo.h b/llvm/include/llvm/CodeGen/GlobalISel/LegacyLegalizerInfo.h
index f6704df3f49d9..3cacdc99dbf8b 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/LegacyLegalizerInfo.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/LegacyLegalizerInfo.h
@@ -465,7 +465,7 @@ class LegacyLegalizerInfo {
ScalarSizeChangeStrategies[LastOp - FirstOp + 1];
SmallVector<SizeChangeStrategy, 1>
VectorElementSizeChangeStrategies[LastOp - FirstOp + 1];
- bool TablesInitialized;
+ bool TablesInitialized = false;
// Data structures used by getAction:
SmallVector<SizeAndActionsVec, 1> ScalarActions[LastOp - FirstOp + 1];
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h b/llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
index 9507c3411b5c8..a0fcb320a380f 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
@@ -403,9 +403,9 @@ class LegalizeRule {
class LegalizeRuleSet {
/// When non-zero, the opcode we are an alias of
- unsigned AliasOf;
+ unsigned AliasOf = 0;
/// If true, there is another opcode that aliases this one
- bool IsAliasedByAnother;
+ bool IsAliasedByAnother = false;
SmallVector<LegalizeRule, 2> Rules;
#ifndef NDEBUG
@@ -556,7 +556,7 @@ class LegalizeRuleSet {
}
public:
- LegalizeRuleSet() : AliasOf(0), IsAliasedByAnother(false) {}
+ LegalizeRuleSet() = default;
bool isAliasedByAnother() { return IsAliasedByAnother; }
void setIsAliasedByAnother() { IsAliasedByAnother = true; }
diff --git a/llvm/include/llvm/CodeGen/IntrinsicLowering.h b/llvm/include/llvm/CodeGen/IntrinsicLowering.h
index 8593f54f39612..06512f2dc5604 100644
--- a/llvm/include/llvm/CodeGen/IntrinsicLowering.h
+++ b/llvm/include/llvm/CodeGen/IntrinsicLowering.h
@@ -24,10 +24,10 @@ class DataLayout;
class IntrinsicLowering {
const DataLayout &DL;
- bool Warned;
+ bool Warned = false;
public:
- explicit IntrinsicLowering(const DataLayout &DL) : DL(DL), Warned(false) {}
+ explicit IntrinsicLowering(const DataLayout &DL) : DL(DL) {}
/// Replace a call to the specified intrinsic function.
/// If an intrinsic function must be implemented by the code generator
diff --git a/llvm/include/llvm/CodeGen/MachineFrameInfo.h b/llvm/include/llvm/CodeGen/MachineFrameInfo.h
index 5df468102a8a3..864ca73180af8 100644
--- a/llvm/include/llvm/CodeGen/MachineFrameInfo.h
+++ b/llvm/include/llvm/CodeGen/MachineFrameInfo.h
@@ -49,14 +49,13 @@ class CalleeSavedInfo {
/// The long-term solution is to model the liveness of callee-saved registers
/// by implicit uses on the return instructions, however, the required
/// changes in the ARM backend would be quite extensive.
- bool Restored;
+ bool Restored = true;
/// Flag indicating whether the register is spilled to stack or another
/// register.
- bool SpilledToReg;
+ bool SpilledToReg = false;
public:
- explicit CalleeSavedInfo(unsigned R, int FI = 0)
- : Reg(R), FrameIdx(FI), Restored(true), SpilledToReg(false) {}
+ explicit CalleeSavedInfo(unsigned R, int FI = 0) : Reg(R), FrameIdx(FI) {}
// Accessors.
Register getReg() const { return Reg; }
@@ -180,14 +179,14 @@ class MachineFrameInfo {
/// If true, the object has been sign-extended.
bool isSExt = false;
- uint8_t SSPLayout;
+ uint8_t SSPLayout = SSPLK_None;
StackObject(uint64_t Size, Align Alignment, int64_t SPOffset,
bool IsImmutable, bool IsSpillSlot, const AllocaInst *Alloca,
bool IsAliased, uint8_t StackID = 0)
: SPOffset(SPOffset), Size(Size), Alignment(Alignment),
isImmutable(IsImmutable), isSpillSlot(IsSpillSlot), StackID(StackID),
- Alloca(Alloca), isAliased(IsAliased), SSPLayout(SSPLK_None) {}
+ Alloca(Alloca), isAliased(IsAliased) {}
};
/// The alignment of the stack.
diff --git a/llvm/include/llvm/CodeGen/MachineModuleSlotTracker.h b/llvm/include/llvm/CodeGen/MachineModuleSlotTracker.h
index 0bd0a31abcae3..fc7635edd82c7 100644
--- a/llvm/include/llvm/CodeGen/MachineModuleSlotTracker.h
+++ b/llvm/include/llvm/CodeGen/MachineModuleSlotTracker.h
@@ -22,7 +22,7 @@ class Module;
class MachineModuleSlotTracker : public ModuleSlotTracker {
const Function &TheFunction;
const MachineModuleInfo &TheMMI;
- unsigned MDNStartSlot, MDNEndSlot;
+ unsigned MDNStartSlot = 0, MDNEndSlot = 0;
void processMachineFunctionMetadata(AbstractSlotTrackerStorage *AST,
const MachineFunction &MF);
diff --git a/llvm/include/llvm/CodeGen/MachineOperand.h b/llvm/include/llvm/CodeGen/MachineOperand.h
index f17904d54cdd7..eded28183ea25 100644
--- a/llvm/include/llvm/CodeGen/MachineOperand.h
+++ b/llvm/include/llvm/CodeGen/MachineOperand.h
@@ -162,7 +162,7 @@ class MachineOperand {
/// ParentMI - This is the instruction that this operand is embedded into.
/// This is valid for all operand types, when the operand is in an instr.
- MachineInstr *ParentMI;
+ MachineInstr *ParentMI = nullptr;
/// Contents union - This contains the payload for the various operand types.
union ContentsUnion {
@@ -200,7 +200,7 @@ class MachineOperand {
} Contents;
explicit MachineOperand(MachineOperandType K)
- : OpKind(K), SubReg_TargetFlags(0), ParentMI(nullptr) {
+ : OpKind(K), SubReg_TargetFlags(0) {
// Assert that the layout is what we expect. It's easy to grow this object.
static_assert(alignof(MachineOperand) <= alignof(int64_t),
"MachineOperand shouldn't be more than 8 byte aligned");
diff --git a/llvm/include/llvm/CodeGen/MachineRegisterInfo.h b/llvm/include/llvm/CodeGen/MachineRegisterInfo.h
index dbabfe5f0f325..94ae6fe02e9c8 100644
--- a/llvm/include/llvm/CodeGen/MachineRegisterInfo.h
+++ b/llvm/include/llvm/CodeGen/MachineRegisterInfo.h
@@ -84,7 +84,7 @@ class MachineRegisterInfo {
/// The flag is true upon \p UpdatedCSRs initialization
/// and false otherwise.
- bool IsUpdatedCSRsInitialized;
+ bool IsUpdatedCSRsInitialized = false;
/// Contains the updated callee saved register list.
/// As opposed to the static list defined in register info,
diff --git a/llvm/include/llvm/CodeGen/SelectionDAGISel.h b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
index 94ba6ad91517a..9cea197724cc6 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAGISel.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
@@ -46,8 +46,8 @@ class SelectionDAGISel : public MachineFunctionPass {
MachineRegisterInfo *RegInfo;
SelectionDAG *CurDAG;
std::unique_ptr<SelectionDAGBuilder> SDB;
- AAResults *AA;
- GCFunctionInfo *GFI;
+ AAResults *AA = nullptr;
+ GCFunctionInfo *GFI = nullptr;
CodeGenOpt::Level OptLevel;
const TargetInstrInfo *TII;
const TargetLowering *TLI;
@@ -199,7 +199,7 @@ class SelectionDAGISel : public MachineFunctionPass {
protected:
/// DAGSize - Size of DAG being instruction selected.
///
- unsigned DAGSize;
+ unsigned DAGSize = 0;
/// ReplaceUses - replace all uses of the old node F with the use
/// of the new node T.
diff --git a/llvm/include/llvm/CodeGen/SlotIndexes.h b/llvm/include/llvm/CodeGen/SlotIndexes.h
index b2133de93ea27..e8d618a24f9ba 100644
--- a/llvm/include/llvm/CodeGen/SlotIndexes.h
+++ b/llvm/include/llvm/CodeGen/SlotIndexes.h
@@ -319,7 +319,7 @@ class raw_ostream;
using IndexList = ilist<IndexListEntry>;
IndexList indexList;
- MachineFunction *mf;
+ MachineFunction *mf = nullptr;
using Mi2IndexMap = DenseMap<const MachineInstr *, SlotIndex>;
Mi2IndexMap mi2iMap;
diff --git a/llvm/include/llvm/CodeGen/SwitchLoweringUtils.h b/llvm/include/llvm/CodeGen/SwitchLoweringUtils.h
index bc22d7789856d..47bedd9befc88 100644
--- a/llvm/include/llvm/CodeGen/SwitchLoweringUtils.h
+++ b/llvm/include/llvm/CodeGen/SwitchLoweringUtils.h
@@ -183,12 +183,12 @@ struct JumpTableHeader {
const Value *SValue;
MachineBasicBlock *HeaderBB;
bool Emitted;
- bool FallthroughUnreachable;
+ bool FallthroughUnreachable = false;
JumpTableHeader(APInt F, APInt L, const Value *SV, MachineBasicBlock *H,
bool E = false)
: First(std::move(F)), Last(std::move(L)), SValue(SV), HeaderBB(H),
- Emitted(E), FallthroughUnreachable(false) {}
+ Emitted(E) {}
};
using JumpTableBlock = std::pair<JumpTableHeader, JumpTable>;
@@ -218,14 +218,14 @@ struct BitTestBlock {
BitTestInfo Cases;
BranchProbability Prob;
BranchProbability DefaultProb;
- bool FallthroughUnreachable;
+ bool FallthroughUnreachable = false;
BitTestBlock(APInt F, APInt R, const Value *SV, unsigned Rg, MVT RgVT, bool E,
bool CR, MachineBasicBlock *P, MachineBasicBlock *D,
BitTestInfo C, BranchProbability Pr)
: First(std::move(F)), Range(std::move(R)), SValue(SV), Reg(Rg),
RegVT(RgVT), Emitted(E), ContiguousRange(CR), Parent(P), Default(D),
- Cases(std::move(C)), Prob(Pr), FallthroughUnreachable(false) {}
+ Cases(std::move(C)), Prob(Pr) {}
};
/// Return the range of values within a range.
diff --git a/llvm/include/llvm/CodeGen/TargetCallingConv.h b/llvm/include/llvm/CodeGen/TargetCallingConv.h
index 7713dd0800c09..62365330379d8 100644
--- a/llvm/include/llvm/CodeGen/TargetCallingConv.h
+++ b/llvm/include/llvm/CodeGen/TargetCallingConv.h
@@ -53,9 +53,9 @@ namespace ISD {
unsigned IsCopyElisionCandidate : 1; ///< Argument copy elision candidate
unsigned IsPointer : 1;
- unsigned ByValOrByRefSize; ///< Byval or byref struct size
+ unsigned ByValOrByRefSize = 0; ///< Byval or byref struct size
- unsigned PointerAddrSpace; ///< Address space of pointer argument
+ unsigned PointerAddrSpace = 0; ///< Address space of pointer argument
public:
ArgFlagsTy()
@@ -65,8 +65,7 @@ namespace ISD {
IsSwiftError(0), IsCFGuardTarget(0), IsHva(0), IsHvaStart(0),
IsSecArgPass(0), MemAlign(0), OrigAlign(0),
IsInConsecutiveRegsLast(0), IsInConsecutiveRegs(0),
- IsCopyElisionCandidate(0), IsPointer(0), ByValOrByRefSize(0),
- PointerAddrSpace(0) {
+ IsCopyElisionCandidate(0), IsPointer(0) {
static_assert(sizeof(*this) == 3 * sizeof(unsigned), "flags are too big");
}
diff --git a/llvm/include/llvm/CodeGen/VirtRegMap.h b/llvm/include/llvm/CodeGen/VirtRegMap.h
index 4953d88340b1b..42e8d294a637a 100644
--- a/llvm/include/llvm/CodeGen/VirtRegMap.h
+++ b/llvm/include/llvm/CodeGen/VirtRegMap.h
@@ -39,10 +39,10 @@ class TargetInstrInfo;
};
private:
- MachineRegisterInfo *MRI;
- const TargetInstrInfo *TII;
- const TargetRegisterInfo *TRI;
- MachineFunction *MF;
+ MachineRegisterInfo *MRI = nullptr;
+ const TargetInstrInfo *TII = nullptr;
+ const TargetRegisterInfo *TRI = nullptr;
+ MachineFunction *MF = nullptr;
/// Virt2PhysMap - This is a virtual to physical register
/// mapping. Each virtual register is required to have an entry in
@@ -72,8 +72,7 @@ class TargetInstrInfo;
static char ID;
VirtRegMap()
- : MachineFunctionPass(ID), MRI(nullptr), TII(nullptr), TRI(nullptr),
- MF(nullptr), Virt2PhysMap(NO_PHYS_REG),
+ : MachineFunctionPass(ID), Virt2PhysMap(NO_PHYS_REG),
Virt2StackSlotMap(NO_STACK_SLOT), Virt2SplitMap(0) {}
VirtRegMap(const VirtRegMap &) = delete;
VirtRegMap &operator=(const VirtRegMap &) = delete;
diff --git a/llvm/lib/CodeGen/AsmPrinter/DIE.cpp b/llvm/lib/CodeGen/AsmPrinter/DIE.cpp
index 1a0256f30d41c..396322c4979d5 100644
--- a/llvm/lib/CodeGen/AsmPrinter/DIE.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/DIE.cpp
@@ -314,8 +314,7 @@ unsigned DIE::computeOffsetsAndAbbrevs(const dwarf::FormParams &FormParams,
//===----------------------------------------------------------------------===//
// DIEUnit Implementation
//===----------------------------------------------------------------------===//
-DIEUnit::DIEUnit(dwarf::Tag UnitTag)
- : Die(UnitTag), Section(nullptr), Offset(0) {
+DIEUnit::DIEUnit(dwarf::Tag UnitTag) : Die(UnitTag) {
Die.Owner = this;
assert((UnitTag == dwarf::DW_TAG_compile_unit ||
UnitTag == dwarf::DW_TAG_skeleton_unit ||
diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfCFIException.cpp b/llvm/lib/CodeGen/AsmPrinter/DwarfCFIException.cpp
index e36b7e2ae885b..63343d2519f94 100644
--- a/llvm/lib/CodeGen/AsmPrinter/DwarfCFIException.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/DwarfCFIException.cpp
@@ -33,8 +33,7 @@
#include "llvm/Target/TargetOptions.h"
using namespace llvm;
-DwarfCFIExceptionBase::DwarfCFIExceptionBase(AsmPrinter *A)
- : EHStreamer(A), shouldEmitCFI(false), hasEmittedCFISections(false) {}
+DwarfCFIExceptionBase::DwarfCFIExceptionBase(AsmPrinter *A) : EHStreamer(A) {}
void DwarfCFIExceptionBase::markFunctionEnd() {
endFragment();
@@ -52,8 +51,7 @@ void DwarfCFIExceptionBase::endFragment() {
}
DwarfCFIException::DwarfCFIException(AsmPrinter *A)
- : DwarfCFIExceptionBase(A), shouldEmitPersonality(false),
- forceEmitPersonality(false), shouldEmitLSDA(false) {}
+ : DwarfCFIExceptionBase(A) {}
DwarfCFIException::~DwarfCFIException() {}
diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfException.h b/llvm/lib/CodeGen/AsmPrinter/DwarfException.h
index 4defa8a30855e..e5cda4739fde7 100644
--- a/llvm/lib/CodeGen/AsmPrinter/DwarfException.h
+++ b/llvm/lib/CodeGen/AsmPrinter/DwarfException.h
@@ -26,9 +26,9 @@ class LLVM_LIBRARY_VISIBILITY DwarfCFIExceptionBase : public EHStreamer {
DwarfCFIExceptionBase(AsmPrinter *A);
/// Per-function flag to indicate if frame CFI info should be emitted.
- bool shouldEmitCFI;
+ bool shouldEmitCFI = false;
/// Per-module flag to indicate if .cfi_section has beeen emitted.
- bool hasEmittedCFISections;
+ bool hasEmittedCFISections = false;
void markFunctionEnd() override;
void endFragment() override;
@@ -36,13 +36,13 @@ class LLVM_LIBRARY_VISIBILITY DwarfCFIExceptionBase : public EHStreamer {
class LLVM_LIBRARY_VISIBILITY DwarfCFIException : public DwarfCFIExceptionBase {
/// Per-function flag to indicate if .cfi_personality should be emitted.
- bool shouldEmitPersonality;
+ bool shouldEmitPersonality = false;
/// Per-function flag to indicate if .cfi_personality must be emitted.
- bool forceEmitPersonality;
+ bool forceEmitPersonality = false;
/// Per-function flag to indicate if .cfi_lsda should be emitted.
- bool shouldEmitLSDA;
+ bool shouldEmitLSDA = false;
public:
//===--------------------------------------------------------------------===//
diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp b/llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
index 15d90c54adfcb..132579aedbc96 100644
--- a/llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
@@ -89,8 +89,7 @@ bool DIEDwarfExpression::isFrameRegister(const TargetRegisterInfo &TRI,
DwarfUnit::DwarfUnit(dwarf::Tag UnitTag, const DICompileUnit *Node,
AsmPrinter *A, DwarfDebug *DW, DwarfFile *DWU)
- : DIEUnit(UnitTag), CUNode(Node), Asm(A), DD(DW), DU(DWU),
- IndexTyDie(nullptr) {}
+ : DIEUnit(UnitTag), CUNode(Node), Asm(A), DD(DW), DU(DWU) {}
DwarfTypeUnit::DwarfTypeUnit(DwarfCompileUnit &CU, AsmPrinter *A,
DwarfDebug *DW, DwarfFile *DWU,
diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfUnit.h b/llvm/lib/CodeGen/AsmPrinter/DwarfUnit.h
index 330f3bacca43b..48d63d126701a 100644
--- a/llvm/lib/CodeGen/AsmPrinter/DwarfUnit.h
+++ b/llvm/lib/CodeGen/AsmPrinter/DwarfUnit.h
@@ -51,7 +51,7 @@ class DwarfUnit : public DIEUnit {
DwarfFile *DU;
/// An anonymous type for index type. Owned by DIEUnit.
- DIE *IndexTyDie;
+ DIE *IndexTyDie = nullptr;
/// Tracks the mapping of unit level debug information variables to debug
/// information entries.
diff --git a/llvm/lib/CodeGen/CodeGenPrepare.cpp b/llvm/lib/CodeGen/CodeGenPrepare.cpp
index 28f24e5ea9088..c888adeafca5d 100644
--- a/llvm/lib/CodeGen/CodeGenPrepare.cpp
+++ b/llvm/lib/CodeGen/CodeGenPrepare.cpp
@@ -3446,7 +3446,7 @@ class AddressingModeCombiner {
bool AllAddrModesTrivial = true;
/// Common Type for all
diff erent fields in addressing modes.
- Type *CommonType;
+ Type *CommonType = nullptr;
/// SimplifyQuery for simplifyInstruction utility.
const SimplifyQuery &SQ;
@@ -3456,7 +3456,7 @@ class AddressingModeCombiner {
public:
AddressingModeCombiner(const SimplifyQuery &_SQ, Value *OriginalValue)
- : CommonType(nullptr), SQ(_SQ), Original(OriginalValue) {}
+ : SQ(_SQ), Original(OriginalValue) {}
/// Get the combined AddrMode
const ExtAddrMode &getAddrMode() const {
diff --git a/llvm/lib/CodeGen/EarlyIfConversion.cpp b/llvm/lib/CodeGen/EarlyIfConversion.cpp
index 0b5469b02637c..6a0da4dad3c16 100644
--- a/llvm/lib/CodeGen/EarlyIfConversion.cpp
+++ b/llvm/lib/CodeGen/EarlyIfConversion.cpp
@@ -111,12 +111,11 @@ class SSAIfConv {
/// Information about each phi in the Tail block.
struct PHIInfo {
MachineInstr *PHI;
- unsigned TReg, FReg;
+ unsigned TReg = 0, FReg = 0;
// Latencies from Cond+Branch, TReg, and FReg to DstReg.
- int CondCycles, TCycles, FCycles;
+ int CondCycles = 0, TCycles = 0, FCycles = 0;
- PHIInfo(MachineInstr *phi)
- : PHI(phi), TReg(0), FReg(0), CondCycles(0), TCycles(0), FCycles(0) {}
+ PHIInfo(MachineInstr *phi) : PHI(phi) {}
};
SmallVector<PHIInfo, 8> PHIs;
diff --git a/llvm/lib/CodeGen/ExpandMemCmp.cpp b/llvm/lib/CodeGen/ExpandMemCmp.cpp
index d0c2b8c267ff2..60ee1812ee2c0 100644
--- a/llvm/lib/CodeGen/ExpandMemCmp.cpp
+++ b/llvm/lib/CodeGen/ExpandMemCmp.cpp
@@ -70,8 +70,8 @@ class MemCmpExpansion {
CallInst *const CI;
ResultBlock ResBlock;
const uint64_t Size;
- unsigned MaxLoadSize;
- uint64_t NumLoadsNonOneByte;
+ unsigned MaxLoadSize = 0;
+ uint64_t NumLoadsNonOneByte = 0;
const uint64_t NumLoadsPerBlockForZeroCmp;
std::vector<BasicBlock *> LoadCmpBlocks;
BasicBlock *EndBlock;
@@ -219,8 +219,7 @@ MemCmpExpansion::MemCmpExpansion(
const TargetTransformInfo::MemCmpExpansionOptions &Options,
const bool IsUsedForZeroCmp, const DataLayout &TheDataLayout,
DomTreeUpdater *DTU)
- : CI(CI), Size(Size), MaxLoadSize(0), NumLoadsNonOneByte(0),
- NumLoadsPerBlockForZeroCmp(Options.NumLoadsPerBlock),
+ : CI(CI), Size(Size), NumLoadsPerBlockForZeroCmp(Options.NumLoadsPerBlock),
IsUsedForZeroCmp(IsUsedForZeroCmp), DL(TheDataLayout), DTU(DTU),
Builder(CI) {
assert(Size > 0 && "zero blocks");
diff --git a/llvm/lib/CodeGen/GlobalISel/LegacyLegalizerInfo.cpp b/llvm/lib/CodeGen/GlobalISel/LegacyLegalizerInfo.cpp
index 727d33fe4a405..6271a4514c272 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegacyLegalizerInfo.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegacyLegalizerInfo.cpp
@@ -64,7 +64,7 @@ raw_ostream &llvm::operator<<(raw_ostream &OS, LegacyLegalizeAction Action) {
return OS;
}
-LegacyLegalizerInfo::LegacyLegalizerInfo() : TablesInitialized(false) {
+LegacyLegalizerInfo::LegacyLegalizerInfo() {
// Set defaults.
// FIXME: these two (G_ANYEXT and G_TRUNC?) can be legalized to the
// fundamental load/store Jakob proposed. Once loads & stores are supported.
diff --git a/llvm/lib/CodeGen/IfConversion.cpp b/llvm/lib/CodeGen/IfConversion.cpp
index 681e2f3dc848b..1b20d1da20ad4 100644
--- a/llvm/lib/CodeGen/IfConversion.cpp
+++ b/llvm/lib/CodeGen/IfConversion.cpp
@@ -1211,11 +1211,11 @@ bool IfConverter::FeasibilityAnalysis(BBInfo &BBI,
void IfConverter::AnalyzeBlock(
MachineBasicBlock &MBB, std::vector<std::unique_ptr<IfcvtToken>> &Tokens) {
struct BBState {
- BBState(MachineBasicBlock &MBB) : MBB(&MBB), SuccsAnalyzed(false) {}
+ BBState(MachineBasicBlock &MBB) : MBB(&MBB) {}
MachineBasicBlock *MBB;
/// This flag is true if MBB's successors have been analyzed.
- bool SuccsAnalyzed;
+ bool SuccsAnalyzed = false;
};
// Push MBB to the stack.
diff --git a/llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp b/llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp
index 2ee9379cb286b..230c6846dde2c 100644
--- a/llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp
+++ b/llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp
@@ -656,10 +656,10 @@ struct VectorInfo {
};
/// Basic-block the load instructions are within
- BasicBlock *BB;
+ BasicBlock *BB = nullptr;
/// Pointer value of all participation load instructions
- Value *PV;
+ Value *PV = nullptr;
/// Participating load instructions
std::set<LoadInst *> LIs;
@@ -668,7 +668,7 @@ struct VectorInfo {
std::set<Instruction *> Is;
/// Final shuffle-vector instruction
- ShuffleVectorInst *SVI;
+ ShuffleVectorInst *SVI = nullptr;
/// Information of the offset for each vector element
ElementInfo *EI;
@@ -676,8 +676,7 @@ struct VectorInfo {
/// Vector Type
FixedVectorType *const VTy;
- VectorInfo(FixedVectorType *VTy)
- : BB(nullptr), PV(nullptr), SVI(nullptr), VTy(VTy) {
+ VectorInfo(FixedVectorType *VTy) : VTy(VTy) {
EI = new ElementInfo[VTy->getNumElements()];
}
diff --git a/llvm/lib/CodeGen/LiveDebugValues/VarLocBasedImpl.cpp b/llvm/lib/CodeGen/LiveDebugValues/VarLocBasedImpl.cpp
index b4dd41bbb8107..42a0967bce3f6 100644
--- a/llvm/lib/CodeGen/LiveDebugValues/VarLocBasedImpl.cpp
+++ b/llvm/lib/CodeGen/LiveDebugValues/VarLocBasedImpl.cpp
@@ -329,7 +329,7 @@ class VarLocBasedLDV : public LDVImpl {
EntryValueKind,
EntryValueBackupKind,
EntryValueCopyBackupKind
- } EVKind;
+ } EVKind = EntryValueLocKind::NonEntryValueKind;
/// The value location. Stored separately to avoid repeatedly
/// extracting it from MI.
@@ -397,8 +397,7 @@ class VarLocBasedLDV : public LDVImpl {
VarLoc(const MachineInstr &MI, LexicalScopes &LS)
: Var(MI.getDebugVariable(), MI.getDebugExpression(),
MI.getDebugLoc()->getInlinedAt()),
- Expr(MI.getDebugExpression()), MI(MI),
- EVKind(EntryValueLocKind::NonEntryValueKind) {
+ Expr(MI.getDebugExpression()), MI(MI) {
assert(MI.isDebugValue() && "not a DBG_VALUE");
assert((MI.isDebugValueList() || MI.getNumOperands() == 4) &&
"malformed DBG_VALUE");
diff --git a/llvm/lib/CodeGen/MachineModuleSlotTracker.cpp b/llvm/lib/CodeGen/MachineModuleSlotTracker.cpp
index e4da179efcc4d..aa63411df9651 100644
--- a/llvm/lib/CodeGen/MachineModuleSlotTracker.cpp
+++ b/llvm/lib/CodeGen/MachineModuleSlotTracker.cpp
@@ -66,8 +66,7 @@ MachineModuleSlotTracker::MachineModuleSlotTracker(
const MachineFunction *MF, bool ShouldInitializeAllMetadata)
: ModuleSlotTracker(MF->getFunction().getParent(),
ShouldInitializeAllMetadata),
- TheFunction(MF->getFunction()), TheMMI(MF->getMMI()), MDNStartSlot(0),
- MDNEndSlot(0) {
+ TheFunction(MF->getFunction()), TheMMI(MF->getMMI()) {
setProcessHook([this](AbstractSlotTrackerStorage *AST, const Module *M,
bool ShouldInitializeAllMetadata) {
this->processMachineModule(AST, M, ShouldInitializeAllMetadata);
diff --git a/llvm/lib/CodeGen/MachineRegisterInfo.cpp b/llvm/lib/CodeGen/MachineRegisterInfo.cpp
index 19bf87d3e2905..1a4ad53ddf81e 100644
--- a/llvm/lib/CodeGen/MachineRegisterInfo.cpp
+++ b/llvm/lib/CodeGen/MachineRegisterInfo.cpp
@@ -43,8 +43,7 @@ void MachineRegisterInfo::Delegate::anchor() {}
MachineRegisterInfo::MachineRegisterInfo(MachineFunction *MF)
: MF(MF), TracksSubRegLiveness(MF->getSubtarget().enableSubRegLiveness() &&
- EnableSubRegLiveness),
- IsUpdatedCSRsInitialized(false) {
+ EnableSubRegLiveness) {
unsigned NumRegs = getTargetRegisterInfo()->getNumRegs();
VRegInfo.reserve(256);
RegAllocHints.reserve(256);
diff --git a/llvm/lib/CodeGen/PostRASchedulerList.cpp b/llvm/lib/CodeGen/PostRASchedulerList.cpp
index d7cd0a583cee2..aac46cb220849 100644
--- a/llvm/lib/CodeGen/PostRASchedulerList.cpp
+++ b/llvm/lib/CodeGen/PostRASchedulerList.cpp
@@ -139,7 +139,7 @@ namespace {
///
/// This is the instruction number from the top of the current block, not
/// the SlotIndex. It is only used by the AntiDepBreaker.
- unsigned EndIndex;
+ unsigned EndIndex = 0;
public:
SchedulePostRATDList(
@@ -206,7 +206,7 @@ SchedulePostRATDList::SchedulePostRATDList(
const RegisterClassInfo &RCI,
TargetSubtargetInfo::AntiDepBreakMode AntiDepMode,
SmallVectorImpl<const TargetRegisterClass *> &CriticalPathRCs)
- : ScheduleDAGInstrs(MF, &MLI), AA(AA), EndIndex(0) {
+ : ScheduleDAGInstrs(MF, &MLI), AA(AA) {
const InstrItineraryData *InstrItins =
MF.getSubtarget().getInstrItineraryData();
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index c73abfd5136b4..57b933c05450d 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -143,7 +143,7 @@ namespace {
SelectionDAG &DAG;
const TargetLowering &TLI;
const SelectionDAGTargetInfo *STI;
- CombineLevel Level;
+ CombineLevel Level = BeforeLegalizeTypes;
CodeGenOpt::Level OptLevel;
bool LegalDAG = false;
bool LegalOperations = false;
@@ -238,8 +238,7 @@ namespace {
public:
DAGCombiner(SelectionDAG &D, AliasAnalysis *AA, CodeGenOpt::Level OL)
: DAG(D), TLI(D.getTargetLoweringInfo()),
- STI(D.getSubtarget().getSelectionDAGInfo()),
- Level(BeforeLegalizeTypes), OptLevel(OL), AA(AA) {
+ STI(D.getSubtarget().getSelectionDAGInfo()), OptLevel(OL), AA(AA) {
ForCodeSize = DAG.shouldOptForSize();
DisableGenericCombines = STI && STI->disableGenericCombines(OptLevel);
diff --git a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
index bfde35935c7b6..d8ef79fe9a7bc 100644
--- a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
@@ -1838,8 +1838,7 @@ FastISel::FastISel(FunctionLoweringInfo &FuncInfo,
TII(*MF->getSubtarget().getInstrInfo()),
TLI(*MF->getSubtarget().getTargetLowering()),
TRI(*MF->getSubtarget().getRegisterInfo()), LibInfo(LibInfo),
- SkipTargetIndependentISel(SkipTargetIndependentISel),
- LastLocalValue(nullptr), EmitStartPt(nullptr) {}
+ SkipTargetIndependentISel(SkipTargetIndependentISel) {}
FastISel::~FastISel() = default;
diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
index 403f345738998..55f6f288f3e3a 100644
--- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
@@ -47,8 +47,7 @@ static cl::opt<int> HighLatencyCycles(
"instructions take for targets with no itinerary"));
ScheduleDAGSDNodes::ScheduleDAGSDNodes(MachineFunction &mf)
- : ScheduleDAG(mf), BB(nullptr), DAG(nullptr),
- InstrItins(mf.getSubtarget().getInstrItineraryData()) {}
+ : ScheduleDAG(mf), InstrItins(mf.getSubtarget().getInstrItineraryData()) {}
/// Run - perform scheduling.
///
@@ -577,7 +576,7 @@ void ScheduleDAGSDNodes::RegDefIter::InitNodeNumDefs() {
// Construct a RegDefIter for this SUnit and find the first valid value.
ScheduleDAGSDNodes::RegDefIter::RegDefIter(const SUnit *SU,
const ScheduleDAGSDNodes *SD)
- : SchedDAG(SD), Node(SU->getNode()), DefIdx(0), NodeNumDefs(0) {
+ : SchedDAG(SD), Node(SU->getNode()) {
InitNodeNumDefs();
Advance();
}
diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
index 8c28ce403c9bd..99bbaeb191821 100644
--- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
+++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
@@ -45,8 +45,8 @@ class InstrItineraryData;
///
class ScheduleDAGSDNodes : public ScheduleDAG {
public:
- MachineBasicBlock *BB;
- SelectionDAG *DAG; // DAG of the current basic block
+ MachineBasicBlock *BB = nullptr;
+ SelectionDAG *DAG = nullptr; // DAG of the current basic block
const InstrItineraryData *InstrItins;
/// The schedule. Null SUnit*'s represent noop instructions.
@@ -138,8 +138,8 @@ class InstrItineraryData;
class RegDefIter {
const ScheduleDAGSDNodes *SchedDAG;
const SDNode *Node;
- unsigned DefIdx;
- unsigned NodeNumDefs;
+ unsigned DefIdx = 0;
+ unsigned NodeNumDefs = 0;
MVT ValueType;
public:
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 77e11b3645887..3c786904620a1 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -319,7 +319,7 @@ SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, CodeGenOpt::Level OL)
CurDAG(new SelectionDAG(tm, OL)),
SDB(std::make_unique<SelectionDAGBuilder>(*CurDAG, *FuncInfo, *SwiftError,
OL)),
- AA(), GFI(), OptLevel(OL), DAGSize(0) {
+ OptLevel(OL) {
initializeGCModuleInfoPass(*PassRegistry::getPassRegistry());
initializeBranchProbabilityInfoWrapperPassPass(
*PassRegistry::getPassRegistry());
diff --git a/llvm/lib/CodeGen/SlotIndexes.cpp b/llvm/lib/CodeGen/SlotIndexes.cpp
index c933031ef37db..ffac68a223bf0 100644
--- a/llvm/lib/CodeGen/SlotIndexes.cpp
+++ b/llvm/lib/CodeGen/SlotIndexes.cpp
@@ -20,7 +20,7 @@ using namespace llvm;
char SlotIndexes::ID = 0;
-SlotIndexes::SlotIndexes() : MachineFunctionPass(ID), mf(nullptr) {
+SlotIndexes::SlotIndexes() : MachineFunctionPass(ID) {
initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
}
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