[llvm] 2cdbaca - [X86] Attempt to fold MOVMSK(CMPEQ(AND(X, C1), 0)) -> MOVMSK(NOT(SHL(X,C2)))
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Sun Jan 30 07:55:24 PST 2022
Author: Simon Pilgrim
Date: 2022-01-30T15:53:21Z
New Revision: 2cdbaca3943a4d6259119f185656328bd3805b68
URL: https://github.com/llvm/llvm-project/commit/2cdbaca3943a4d6259119f185656328bd3805b68
DIFF: https://github.com/llvm/llvm-project/commit/2cdbaca3943a4d6259119f185656328bd3805b68.diff
LOG: [X86] Attempt to fold MOVMSK(CMPEQ(AND(X,C1),0)) -> MOVMSK(NOT(SHL(X,C2)))
Allows pow2 mask tests to avoid an unnecessary constant load.
Noticed while investigating how to extend MatchVectorAllZeroTest to support more allof/anyof patterns.
Added:
Modified:
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/test/CodeGen/X86/combine-movmsk.ll
llvm/test/CodeGen/X86/vector-reduce-or-cmp.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index e0c4a04e00840..c032e523e5634 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -51181,6 +51181,30 @@ static SDValue combineMOVMSK(SDNode *N, SelectionDAG &DAG,
DAG.getConstant(NotMask, DL, VT));
}
+ // Fold movmsk(icmp_eq(and(x,c1),0)) -> movmsk(not(shl(x,c2)))
+ // iff pow2splat(c1).
+ if (Src.getOpcode() == X86ISD::PCMPEQ &&
+ Src.getOperand(0).getOpcode() == ISD::AND &&
+ ISD::isBuildVectorAllZeros(Src.getOperand(1).getNode())) {
+ SDValue LHS = Src.getOperand(0).getOperand(0);
+ SDValue RHS = Src.getOperand(0).getOperand(1);
+ KnownBits KnownRHS = DAG.computeKnownBits(RHS);
+ if (KnownRHS.isConstant() && KnownRHS.getConstant().isPowerOf2()) {
+ SDLoc DL(N);
+ MVT ShiftVT = SrcVT;
+ if (ShiftVT.getScalarType() == MVT::i8) {
+ // vXi8 shifts - we only care about the signbit so can use PSLLW.
+ ShiftVT = MVT::getVectorVT(MVT::i16, NumElts / 2);
+ LHS = DAG.getBitcast(ShiftVT, LHS);
+ }
+ unsigned ShiftAmt = KnownRHS.getConstant().countLeadingZeros();
+ LHS = getTargetVShiftByConstNode(X86ISD::VSHLI, DL, ShiftVT, LHS,
+ ShiftAmt, DAG);
+ LHS = DAG.getNOT(DL, DAG.getBitcast(SrcVT, LHS), SrcVT);
+ return DAG.getNode(X86ISD::MOVMSK, DL, VT, LHS);
+ }
+ }
+
// Simplify the inputs.
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
APInt DemandedMask(APInt::getAllOnes(NumBits));
diff --git a/llvm/test/CodeGen/X86/combine-movmsk.ll b/llvm/test/CodeGen/X86/combine-movmsk.ll
index b91371742de25..0005a9968e37c 100644
--- a/llvm/test/CodeGen/X86/combine-movmsk.ll
+++ b/llvm/test/CodeGen/X86/combine-movmsk.ll
@@ -220,7 +220,7 @@ define i1 @pmovmskb_noneof_v16i8_positive(<16 x i8> %a0) {
ret i1 %4
}
-; TODO: MOVMSK(CMPEQ(AND(X,C1),0)) -> MOVMSK(NOT(SHL(X,C2)))
+; MOVMSK(CMPEQ(AND(X,C1),0)) -> MOVMSK(NOT(SHL(X,C2)))
define i32 @movmskpd_pow2_mask(<2 x i64> %a0) {
; SSE2-LABEL: movmskpd_pow2_mask:
; SSE2: # %bb.0:
@@ -234,18 +234,14 @@ define i32 @movmskpd_pow2_mask(<2 x i64> %a0) {
;
; SSE42-LABEL: movmskpd_pow2_mask:
; SSE42: # %bb.0:
-; SSE42-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; SSE42-NEXT: pxor %xmm1, %xmm1
-; SSE42-NEXT: pcmpeqq %xmm0, %xmm1
-; SSE42-NEXT: movmskpd %xmm1, %eax
+; SSE42-NEXT: movmskpd %xmm0, %eax
+; SSE42-NEXT: xorl $3, %eax
; SSE42-NEXT: retq
;
; AVX-LABEL: movmskpd_pow2_mask:
; AVX: # %bb.0:
-; AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
-; AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1
-; AVX-NEXT: vpcmpeqq %xmm1, %xmm0, %xmm0
; AVX-NEXT: vmovmskpd %xmm0, %eax
+; AVX-NEXT: xorl $3, %eax
; AVX-NEXT: retq
%1 = and <2 x i64> %a0, <i64 -9223372036854775808, i64 -9223372036854775808>
%2 = icmp eq <2 x i64> %1, zeroinitializer
@@ -258,10 +254,9 @@ define i32 @movmskpd_pow2_mask(<2 x i64> %a0) {
define i32 @movmskps_pow2_mask(<4 x i32> %a0) {
; SSE-LABEL: movmskps_pow2_mask:
; SSE: # %bb.0:
-; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; SSE-NEXT: pxor %xmm1, %xmm1
-; SSE-NEXT: pcmpeqd %xmm0, %xmm1
-; SSE-NEXT: movmskps %xmm1, %eax
+; SSE-NEXT: pslld $29, %xmm0
+; SSE-NEXT: movmskps %xmm0, %eax
+; SSE-NEXT: xorl $15, %eax
; SSE-NEXT: retq
%1 = and <4 x i32> %a0, <i32 4, i32 4, i32 4, i32 4>
%2 = icmp eq <4 x i32> %1, zeroinitializer
@@ -274,18 +269,16 @@ define i32 @movmskps_pow2_mask(<4 x i32> %a0) {
define i32 @pmovmskb_pow2_mask(<16 x i8> %a0) {
; SSE-LABEL: pmovmskb_pow2_mask:
; SSE: # %bb.0:
-; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; SSE-NEXT: pxor %xmm1, %xmm1
-; SSE-NEXT: pcmpeqb %xmm0, %xmm1
-; SSE-NEXT: pmovmskb %xmm1, %eax
+; SSE-NEXT: psllw $7, %xmm0
+; SSE-NEXT: pmovmskb %xmm0, %eax
+; SSE-NEXT: xorl $65535, %eax # imm = 0xFFFF
; SSE-NEXT: retq
;
; AVX-LABEL: pmovmskb_pow2_mask:
; AVX: # %bb.0:
-; AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
-; AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1
-; AVX-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0
+; AVX-NEXT: vpsllw $7, %xmm0, %xmm0
; AVX-NEXT: vpmovmskb %xmm0, %eax
+; AVX-NEXT: xorl $65535, %eax # imm = 0xFFFF
; AVX-NEXT: retq
%1 = and <16 x i8> %a0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
%2 = icmp eq <16 x i8> %1, zeroinitializer
diff --git a/llvm/test/CodeGen/X86/vector-reduce-or-cmp.ll b/llvm/test/CodeGen/X86/vector-reduce-or-cmp.ll
index 31cbb9a1afefa..59c7db337fd2a 100644
--- a/llvm/test/CodeGen/X86/vector-reduce-or-cmp.ll
+++ b/llvm/test/CodeGen/X86/vector-reduce-or-cmp.ll
@@ -951,10 +951,9 @@ define i1 @mask_v128i8(<128 x i8> %a0) {
; SSE2-NEXT: por %xmm4, %xmm2
; SSE2-NEXT: por %xmm3, %xmm2
; SSE2-NEXT: por %xmm0, %xmm2
-; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
-; SSE2-NEXT: pxor %xmm0, %xmm0
-; SSE2-NEXT: pcmpeqb %xmm2, %xmm0
-; SSE2-NEXT: pmovmskb %xmm0, %eax
+; SSE2-NEXT: psllw $7, %xmm2
+; SSE2-NEXT: pmovmskb %xmm2, %eax
+; SSE2-NEXT: xorl $65535, %eax # imm = 0xFFFF
; SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF
; SSE2-NEXT: sete %al
; SSE2-NEXT: retq
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