[PATCH] D118561: [AArch64] Add legal types for Streaming SVE

Cullen Rhodes via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Sun Jan 30 04:40:41 PST 2022


c-rhodes created this revision.
c-rhodes added reviewers: sdesmalen, kmclaughlin, david-arm, CarolineConcatto.
Herald added subscribers: ctetreau, hiraditya, kristof.beyls, tschuett.
c-rhodes requested review of this revision.
Herald added a subscriber: alextsao1999.
Herald added a project: LLVM.

The compiler currently crashes for scalable types when compiling with
+sme, e.g.

  define <vscale x 4 x i32> @foo(<vscale x 4 x i32> %a) {
    ret <vscale x 4 x i32> %a
  }

since it doesn't know how to legalize the types. SME implies a subset of
SVE (+streaming-sve), the hasSVE predication in the backend needs
extending to consider types/operations that are legal in Streaming SVE.

This is the first patch adding legal types <-> register classes. Before
making the change +sve(2) was temporarily replaced with +sme in all the
intrinsics tests to see what failed, and again after making the change.
For all the tests that passed after adding the legal types another RUN
line has been added for +streaming-sve. More patches to follow.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D118561

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/sve-intrinsics-contiguous-prefetches.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-conversion.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-counting-bits.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-counting-elems.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-fp-converts.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-ldN-reg+imm-addr-mode.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-ldN-reg+reg-addr-mode.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-ldN-sret-reg+imm-addr-mode.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-ldN-sret-reg+reg-addr-mode.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-logical.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-pred-creation.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-pred-testing.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-reinterpret.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-reversal.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-sel.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-sqdec.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-sqinc.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-st1-addressing-mode-reg-imm.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-st1-addressing-mode-reg-reg.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-st1.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-stN-reg-imm-addr-mode.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-stN-reg-reg-addr-mode.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-stores.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-uqdec.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-uqinc.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-while.ll
  llvm/test/CodeGen/AArch64/sve2-intrinsics-binary-narrowing-add-sub.ll
  llvm/test/CodeGen/AArch64/sve2-intrinsics-binary-narrowing-shr.ll
  llvm/test/CodeGen/AArch64/sve2-intrinsics-complex-dot.ll
  llvm/test/CodeGen/AArch64/sve2-intrinsics-contiguous-conflict-detection.ll
  llvm/test/CodeGen/AArch64/sve2-intrinsics-fp-converts.ll
  llvm/test/CodeGen/AArch64/sve2-intrinsics-fp-int-binary-logarithm.ll
  llvm/test/CodeGen/AArch64/sve2-intrinsics-fp-widening-mul-acc.ll
  llvm/test/CodeGen/AArch64/sve2-intrinsics-int-mul-lane.ll
  llvm/test/CodeGen/AArch64/sve2-intrinsics-non-widening-pairwise-arith.ll
  llvm/test/CodeGen/AArch64/sve2-intrinsics-polynomial-arithmetic.ll
  llvm/test/CodeGen/AArch64/sve2-intrinsics-unary-narrowing.ll
  llvm/test/CodeGen/AArch64/sve2-intrinsics-uniform-complex-arith.ll
  llvm/test/CodeGen/AArch64/sve2-intrinsics-while.ll
  llvm/test/CodeGen/AArch64/sve2-intrinsics-widening-complex-int-arith.ll
  llvm/test/CodeGen/AArch64/sve2-intrinsics-widening-dsp.ll
  llvm/test/CodeGen/AArch64/sve2-intrinsics-widening-pairwise-arith.ll

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