[PATCH] D118461: [AMDGPU] Introduce new ISel combine for trunc-slr patterns

[Thomas Symalla via Phabricator via llvm-commits]

tsymalla added inline comments.


================
Comment at: llvm/test/CodeGen/AMDGPU/dagcombine-lshr-and-cmp.ll:12
+  %2 = xor i1 %1, -1
+  br i1 %2, label %out.true, label %out.else
+
----------------
arsenm wrote:
> Don't need control flow in this test. Also should test pattern for scalar and vector inputs
The control flow was used to prevent having the truncate in the SDag optimized away (which is used as part of the pattern match here). I  am going to check if the adjustments to the test (check comment from @foad) are going to help here.
Going to test additional cases in the new revision.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D118461/new/

https://reviews.llvm.org/D118461