[llvm] 6297f92 - [RISCV] Fix FileCheck prefixes in RVV test
Fraser Cormack via llvm-commits
llvm-commits at lists.llvm.org
Fri Jan 28 04:19:02 PST 2022
Author: Fraser Cormack
Date: 2022-01-28T12:08:30Z
New Revision: 6297f929f73134736fadf704056fda3dee4ace9b
URL: https://github.com/llvm/llvm-project/commit/6297f929f73134736fadf704056fda3dee4ace9b
DIFF: https://github.com/llvm/llvm-project/commit/6297f929f73134736fadf704056fda3dee4ace9b.diff
LOG: [RISCV] Fix FileCheck prefixes in RVV test
The LMULMAX check names didn't match the options we were passing to llc
(they were swapped around) and we were silently missing coverage for one
test which differs between RV32 and RV64.
Added:
Modified:
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
index d1a5b516d7f9c..a7cf5237ad295 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
@@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1
-; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1
-; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2
-; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2
+; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,LMULMAX1
+; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,LMULMAX1
+; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,LMULMAX2
+; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,LMULMAX2
; Tests that a floating-point build_vector doesn't try and generate a VID
; instruction
@@ -35,45 +35,45 @@ define void @buildvec_no_vid_v4f32(<4 x float>* %x) {
define <4 x float> @hang_when_merging_stores_after_legalization(<8 x float> %x, <8 x float> %y) optsize {
; LMULMAX1-LABEL: hang_when_merging_stores_after_legalization:
; LMULMAX1: # %bb.0:
-; LMULMAX1-NEXT: addi sp, sp, -32
-; LMULMAX1-NEXT: .cfi_def_cfa_offset 32
-; LMULMAX1-NEXT: vsetivli zero, 0, e32, m2, ta, mu
-; LMULMAX1-NEXT: vfmv.f.s ft0, v10
-; LMULMAX1-NEXT: fsw ft0, 24(sp)
-; LMULMAX1-NEXT: vfmv.f.s ft0, v8
-; LMULMAX1-NEXT: fsw ft0, 16(sp)
-; LMULMAX1-NEXT: vsetivli zero, 1, e32, m2, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v10, v10, 7
-; LMULMAX1-NEXT: vfmv.f.s ft0, v10
-; LMULMAX1-NEXT: fsw ft0, 28(sp)
-; LMULMAX1-NEXT: vslidedown.vi v8, v8, 7
-; LMULMAX1-NEXT: vfmv.f.s ft0, v8
-; LMULMAX1-NEXT: fsw ft0, 20(sp)
+; LMULMAX1-NEXT: li a0, 2
+; LMULMAX1-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
+; LMULMAX1-NEXT: vmv.s.x v0, a0
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-NEXT: addi a0, sp, 16
-; LMULMAX1-NEXT: vle32.v v8, (a0)
-; LMULMAX1-NEXT: addi sp, sp, 32
+; LMULMAX1-NEXT: vrgather.vi v12, v8, 0
+; LMULMAX1-NEXT: vrgather.vi v12, v9, 3, v0.t
+; LMULMAX1-NEXT: li a0, 8
+; LMULMAX1-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
+; LMULMAX1-NEXT: vmv.s.x v0, a0
+; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
+; LMULMAX1-NEXT: vrgather.vi v8, v10, 0
+; LMULMAX1-NEXT: vrgather.vi v8, v11, 3, v0.t
+; LMULMAX1-NEXT: li a0, 3
+; LMULMAX1-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
+; LMULMAX1-NEXT: vmv.s.x v0, a0
+; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
+; LMULMAX1-NEXT: vmerge.vvm v8, v8, v12, v0
; LMULMAX1-NEXT: ret
;
; LMULMAX2-LABEL: hang_when_merging_stores_after_legalization:
; LMULMAX2: # %bb.0:
-; LMULMAX2-NEXT: li a0, 2
-; LMULMAX2-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
-; LMULMAX2-NEXT: vmv.s.x v0, a0
-; LMULMAX2-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX2-NEXT: vrgather.vi v12, v8, 0
-; LMULMAX2-NEXT: vrgather.vi v12, v9, 3, v0.t
-; LMULMAX2-NEXT: li a0, 8
-; LMULMAX2-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
-; LMULMAX2-NEXT: vmv.s.x v0, a0
+; LMULMAX2-NEXT: addi sp, sp, -32
+; LMULMAX2-NEXT: .cfi_def_cfa_offset 32
+; LMULMAX2-NEXT: vsetivli zero, 0, e32, m2, ta, mu
+; LMULMAX2-NEXT: vfmv.f.s ft0, v10
+; LMULMAX2-NEXT: fsw ft0, 24(sp)
+; LMULMAX2-NEXT: vfmv.f.s ft0, v8
+; LMULMAX2-NEXT: fsw ft0, 16(sp)
+; LMULMAX2-NEXT: vsetivli zero, 1, e32, m2, ta, mu
+; LMULMAX2-NEXT: vslidedown.vi v10, v10, 7
+; LMULMAX2-NEXT: vfmv.f.s ft0, v10
+; LMULMAX2-NEXT: fsw ft0, 28(sp)
+; LMULMAX2-NEXT: vslidedown.vi v8, v8, 7
+; LMULMAX2-NEXT: vfmv.f.s ft0, v8
+; LMULMAX2-NEXT: fsw ft0, 20(sp)
; LMULMAX2-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX2-NEXT: vrgather.vi v8, v10, 0
-; LMULMAX2-NEXT: vrgather.vi v8, v11, 3, v0.t
-; LMULMAX2-NEXT: li a0, 3
-; LMULMAX2-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
-; LMULMAX2-NEXT: vmv.s.x v0, a0
-; LMULMAX2-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX2-NEXT: vmerge.vvm v8, v8, v12, v0
+; LMULMAX2-NEXT: addi a0, sp, 16
+; LMULMAX2-NEXT: vle32.v v8, (a0)
+; LMULMAX2-NEXT: addi sp, sp, 32
; LMULMAX2-NEXT: ret
%z = shufflevector <8 x float> %x, <8 x float> %y, <4 x i32> <i32 0, i32 7, i32 8, i32 15>
ret <4 x float> %z
@@ -168,6 +168,31 @@ define void @buildvec_dominant2_v4f32(<4 x float>* %x, float %f) {
}
define void @buildvec_merge0_v4f32(<4 x float>* %x, float %f) {
+; RV32-LABEL: buildvec_merge0_v4f32:
+; RV32: # %bb.0:
+; RV32-NEXT: li a1, 6
+; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
+; RV32-NEXT: lui a2, %hi(.LCPI7_0)
+; RV32-NEXT: flw ft0, %lo(.LCPI7_0)(a2)
+; RV32-NEXT: vmv.s.x v0, a1
+; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
+; RV32-NEXT: vfmv.v.f v8, fa0
+; RV32-NEXT: vfmerge.vfm v8, v8, ft0, v0
+; RV32-NEXT: vse32.v v8, (a0)
+; RV32-NEXT: ret
+;
+; RV64-LABEL: buildvec_merge0_v4f32:
+; RV64: # %bb.0:
+; RV64-NEXT: lui a1, %hi(.LCPI7_0)
+; RV64-NEXT: flw ft0, %lo(.LCPI7_0)(a1)
+; RV64-NEXT: li a1, 6
+; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
+; RV64-NEXT: vmv.s.x v0, a1
+; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
+; RV64-NEXT: vfmv.v.f v8, fa0
+; RV64-NEXT: vfmerge.vfm v8, v8, ft0, v0
+; RV64-NEXT: vse32.v v8, (a0)
+; RV64-NEXT: ret
%v0 = insertelement <4 x float> undef, float %f, i32 0
%v1 = insertelement <4 x float> %v0, float 2.0, i32 1
%v2 = insertelement <4 x float> %v1, float 2.0, i32 2
More information about the llvm-commits
mailing list