[PATCH] D118133: [AArch64] Expand UADDLV patterns to SADDLV

[Alexandros Lamprineas via Phabricator via llvm-commits]

labrinea accepted this revision.
labrinea added inline comments.
This revision is now accepted and ready to land.


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Comment at: llvm/lib/Target/AArch64/AArch64InstrInfo.td:5881
+}
+
+defm : SIMDAcrossLaneLongPairIntrinsic<"UADDLV", AArch64uaddlp>;
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dmgreen wrote:
> labrinea wrote:
> > We seem to have patterns for all of `8B, 16B, 8H, 4H and 4S` if I read this right. I am seeing tests (in the diff at least) that only cover `4S, 8H and 16B` (datasize = 128). Do we have/need tests for the rest (datasize = 64)?
> Yeah some of the extending vecreduce patterns don't simplify in the same way. Those will have to be left for another patch though. I've made sure there is test coverage.
Alright, looks good.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D118133/new/

https://reviews.llvm.org/D118133