[PATCH] D117389: [RISCV] Improve extract_vector_elt for fixed mask registers.

[Jianjian Guan via Phabricator via llvm-commits]

jacquesguan added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:4270
+        if (NumElts <= LargestEltVT.getSizeInBits()) {
+          WideEltVT = MVT::getIntegerVT(NumElts);
+          WidenVecLen = 1;
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frasercrmck wrote:
> I think asserting that `NumElts` is a power of two (or just skipping this optimization) would be useful just in case we ever support other vector types. This is quite an edge case so won't be well covered, and could silently do some weird things.
Thanks, I add an assert for this.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117389/new/

https://reviews.llvm.org/D117389