[PATCH] D118406: [RISCV] Preserve VL when truncating i64 gather/scatter indices on RV32.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll:966
 ; RV32-NEXT:    vsext.vf8 v12, v8
 ; RV32-NEXT:    vsll.vi v8, v12, 3
+; RV32-NEXT:    vsetvli zero, a1, e32, m2, ta, mu
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We still forgot to use the correct VL for the scaling shift. I'll forgive the vsext since we don't have a VP intrinsic yet.


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Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll:968
+; RV32-NEXT:    vsetvli zero, a1, e32, m2, ta, mu
 ; RV32-NEXT:    vnsrl.wx v12, v8, zero
+; RV32-NEXT:    vsetvli zero, zero, e64, m4, ta, mu
----------------
Ideally we'd shrink the vsext to i32 before the shift and avoid this vnsrl.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D118406/new/

https://reviews.llvm.org/D118406