[PATCH] D118367: [AMDGPU] SILoadStoreOptimizer: use separate lists for AGPR instructions

[Jay Foad via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG94a4594c5483: [AMDGPU] SILoadStoreOptimizer: use separate lists for AGPR instructions (authored by foad).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D118367/new/

https://reviews.llvm.org/D118367

Files:
  llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp


Index: llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
+++ llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
@@ -105,6 +105,7 @@
     unsigned DMask;
     InstClassEnum InstClass;
     unsigned CPol = 0;
+    bool IsAGPR;
     bool UseST64;
     int AddrIdx[MaxAddressRegs];
     const MachineOperand *AddrReg[MaxAddressRegs];
@@ -491,6 +492,8 @@
   if (InstClass == UNKNOWN)
     return;
 
+  IsAGPR = LSO.TRI->hasAGPRs(LSO.getDataRegClass(*MI));
+
   switch (InstClass) {
   case DS_READ:
    EltSize =
@@ -912,9 +915,6 @@
   DenseSet<Register> PhysRegUsesToMove;
   addDefsUsesToList(*CI.I, RegDefsToMove, PhysRegUsesToMove);
 
-  const TargetRegisterClass *DataRC = getDataRegClass(*CI.I);
-  bool IsAGPR = TRI->hasAGPRs(DataRC);
-
   MachineBasicBlock::iterator E = std::next(Paired.I);
   MachineBasicBlock::iterator MBBI = std::next(CI.I);
   MachineBasicBlock::iterator MBBE = CI.I->getParent()->end();
@@ -974,15 +974,13 @@
       continue;
 
     if (&*MBBI == &*Paired.I) {
-      if (TRI->hasAGPRs(getDataRegClass(*MBBI)) != IsAGPR)
-        return false;
       // FIXME: nothing is illegal in a ds_write2 opcode with two AGPR data
       //        operands. However we are reporting that ds_write2 shall have
       //        only VGPR data so that machine copy propagation does not
       //        create an illegal instruction with a VGPR and AGPR sources.
       //        Consequenctially if we create such instruction the verifier
       //        will complain.
-      if (IsAGPR && CI.InstClass == DS_WRITE)
+      if (CI.IsAGPR && CI.InstClass == DS_WRITE)
         return false;
 
       // We need to go through the list of instructions that we plan to
@@ -1959,6 +1957,7 @@
                  std::list<std::list<CombineInfo> > &MergeableInsts) const {
   for (std::list<CombineInfo> &AddrList : MergeableInsts) {
     if (AddrList.front().InstClass == CI.InstClass &&
+        AddrList.front().IsAGPR == CI.IsAGPR &&
         AddrList.front().hasSameBaseAddress(*CI.I)) {
       AddrList.emplace_back(CI);
       return;


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