[PATCH] D117900: [AArch64][SVE] Fold gather/scatter with 32bits when possible

[Caroline via Phabricator via llvm-commits]

CarolineConcatto added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:16145
+    if (auto Shift = DAG.getSplatValue(Index.getOperand(1)))
+      if (auto Offset = DAG.getSplatValue(Index.getOperand(0).getOperand(0))) {
+        auto *C = dyn_cast<ConstantSDNode>(Shift);
----------------
CarolineConcatto wrote:
> sdesmalen wrote:
> > This isn't very easy to read, I'd recommend creating three variables instead:
> > 
> >   if (Index.getOpcode() == ISD::SHL &&
> >       Index.getOperand(0).getOpcode() == ISD::ADD &&
> >       Index.getOperand(0).getOperand(1).getOpcode() == ISD::STEP_VECTOR) {
> >     SDValue ShiftAmount = Index.getOperand(1);              
> >     SDValue BaseOffset = Index.getOperand(0).getOperand(0); 
> >     SDValue Step = Index.getOperand(0).getOperand(1);       
> >     if (auto Shift = DAG.getSplatValue(ShiftAmount))        
> >       if (auto *ShiftC = dyn_cast<ConstantSDNode>(Shift))   
> >         if (auto Offset = DAG.getSplatValue(BaseOffset)) {  
> >            // ... code to calculate Stride, Offset and BasePtr here ...
> I pushed this fold to be in a second patch, maybe it will be better to review.
> In case not I will add these extra variables.
This fold is now here:
https://reviews.llvm.org/D118345


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117900/new/

https://reviews.llvm.org/D117900