[PATCH] D113291: [AggressiveInstCombine] Lower Table Based CTTZ and enable it for AARCH64 in -O3

[Djordje Todorovic via Phabricator via llvm-commits]

djtodoro added a comment.

In D113291#3275222 <https://reviews.llvm.org/D113291#3275222>, @dmgreen wrote:

>> I have a small query regarding this patch. The patch emits following llvm assembly for ctz table -
>>
>> -----Patch assembly-------
>> // %bb.0:
>>
>>   rbit w8, w0
>>   cmp w0, #0
>>   clz w8, w8
>>   csel w0, wzr, w8, eq
>>   ret
>>
>> ----------------------------------
>>
>> but in gcc, we have the following assembly being emitted -
>>
>> ------------GCC---------------------
>> f(unsigned int):
>>
>>   rbit    w0, w0
>>   clz     w0, w0
>>   and     w0, w0, 31
>>   ret
>>
>> ------------------------------------------
>
> That sounds like a backend optimization that could happen given we know the semantics of the AArch64 instruction.

Yep, +1 for this. I'd leave this job to backends.


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