[PATCH] D118333: [RISCV] Update computeTargetABI implementation.

[Zakk Chen via Phabricator via llvm-commits]

khchen created this revision.
khchen added reviewers: craig.topper, jrtc27, frasercrmck, kito-cheng, arcbbb, monkchiang, eopXD.
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I think it's good to have one logic to get the default
target-abi if no explicit ABI is given, because currently
we have two different logic in front-end and back-end.

The front-end is defautl to the ilp32/ilp32e/lp64 ABI, and
ilp32d/lp64d when hardware support for extension D.
The backend is default to the ilp32/ilp32e/lp64 ABI.

Due to the default target-abi had changed, I update some tests
by specific the target-abi with old default value to make the
expected result unchanged.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D118333

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/include/llvm/Support/TargetParser.h
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Support/TargetParser.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
  llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll
  llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll
  llvm/test/CodeGen/RISCV/double-calling-conv.ll
  llvm/test/CodeGen/RISCV/double-imm.ll
  llvm/test/CodeGen/RISCV/double-mem.ll
  llvm/test/CodeGen/RISCV/double-previous-failure.ll
  llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll
  llvm/test/CodeGen/RISCV/fastcc-float.ll
  llvm/test/CodeGen/RISCV/float-bit-preserving-dagcombines.ll
  llvm/test/CodeGen/RISCV/fpclamptosat.ll
  llvm/test/CodeGen/RISCV/fpclamptosat_vec.ll
  llvm/test/CodeGen/RISCV/frm-dependency.ll
  llvm/test/CodeGen/RISCV/inline-asm-clobbers.ll
  llvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll
  llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll
  llvm/test/CodeGen/RISCV/mattr-invalid-combination.ll
  llvm/test/CodeGen/RISCV/rv64d-double-convert-strict.ll
  llvm/test/CodeGen/RISCV/rv64d-double-convert.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-emergency-slot.mir
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll
  llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir
  llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
  llvm/test/CodeGen/RISCV/rvv/vmfeq-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmfeq-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmfge-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmfge-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmfgt-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmfgt-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmfle-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmfle-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmflt-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmflt-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmfne-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmfne-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
  llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
  llvm/test/CodeGen/RISCV/select-const.ll
  llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
  llvm/test/CodeGen/RISCV/spill-fpr-scalar.ll

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