[PATCH] D117954: [RISCV] Add DAG combines to transform ADD_VL/SUB_VL into widening add/sub.

[Roger Ferrer Ibanez via Phabricator via llvm-commits]

rogfer01 added a comment.
Herald added a subscriber: pcwang-thead.

Just to confirm, this is not fixed vector specific, is it?

If this is the case could you add some tests for those?



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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:7261
+
+  // Determine the narrow size for a widening multiply.
+  unsigned NarrowSize = VT.getScalarSizeInBits() / 2;
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I'm confused by this reference to "widening multiply". I fail to see anything about widening multiplies in this patch.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:7345
+    // See if have enough sign bits or zero bits in the scalar to use a
+    // widening multiply by splatting to smaller element size.
+    unsigned EltBits = VT.getScalarSizeInBits();
----------------
Ditto.


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https://reviews.llvm.org/D117954