[PATCH] D118316: [PowerPC] Materialize special ConstantFP using instructions instead of load from TOC

Ting Wang via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Jan 26 22:26:09 PST 2022


tingwang added inline comments.


================
Comment at: llvm/test/CodeGen/PowerPC/handle-f16-storage-type.ll:1255
 ; CHECK-NEXT:    fcmpu cr0, f0, f1
-; CHECK-NEXT:    beqlr cr0
+; CHECK-NEXT:    beq cr0, .LBB20_2
 ; CHECK-NEXT:  # %bb.1:
----------------
"beqlr 0" converted into "beq 0, .LBB0_2; .LBB0_2: blr" sequence, introduced dummy jump. This maybe one issue.


================
Comment at: llvm/test/CodeGen/PowerPC/scalar_cmp.ll:908
+; FAST-P9-NEXT:    xvcvsxwdp vs0, vs34
+; FAST-P9-NEXT:    xsadddp f0, f1, f0
 ; FAST-P9-NEXT:    fsel f1, f0, f2, f3
----------------
Given the operand is known and isFPImmLegal(<negative>) is checked, fsub is converted into fadd. 
Combining: t15: f64 = fsub t2, ConstantFP:f64<1.000000e+00>
Creating fp constant: t17: f64 = ConstantFP<-1.000000e+00>
Creating new node: t18: f64 = fadd t2, ConstantFP:f64<-1.000000e+00>
 ... into: t18: f64 = fadd t2, ConstantFP:f64<-1.000000e+00>



================
Comment at: llvm/test/CodeGen/PowerPC/scalar_cmp.ll:932
 ; NO-FAST-P9-NEXT:  # %bb.1: # %entry
+; NO-FAST-P9-NEXT:    fcmpu cr0, f1, f1
+; NO-FAST-P9-NEXT:    bc 12, un, .LBB24_3
----------------
This maybe one issue:
Given below DAG:
        t16: i1 = setcc t2, ConstantFP:f64<1.000000e+00>, setlt:ch                                               
        t18: i1 = setcc t2, ConstantFP:f64<1.000000e+00>, setuo:ch                                                          
      t19: i1 = or t16, t18      

Some logic optimized the second setcc:
Combining: t18: i1 = setcc t2, ConstantFP:f64<1.000000e+00>, setuo:ch
Creating new node: t23: i1 = setcc t2, t2, setuo:ch

So that resulted two statements which should have been executed in one fcmpu if there is no combine.
        t16: i1 = setcc t2, ConstantFP:f64<1.000000e+00>, setlt:ch
        t23: i1 = setcc t2, t2, setuo:ch
      t19: i1 = or t16, t23


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D118316/new/

https://reviews.llvm.org/D118316



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