[PATCH] D116915: [DAGCombiner][AArch64] Enhance to support for scalar CSINC

[Allen zhong via Phabricator via llvm-commits]

Allen added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:14630
+
+  if (!CSel.hasOneUse() || !RHS.hasOneUse())
+    return SDValue();
----------------
dmgreen wrote:
> I don't think it matters if the RHS has more than 1 use, it should still be OK to transform as we only use the value in another expression.
I had delete the condition !RHS.hasOneUse(), but recently  the upstream may has some regression, it doen't finish the precommit build checking.  so may  I need wait a moment  to figure out that issue ?


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:14633-14636
+  SDValue CCVal = CSel.getOperand(2);
+  ConstantSDNode *CC = cast<ConstantSDNode>(CCVal);
+  AArch64CC::CondCode AArch64CC =
+      static_cast<AArch64CC::CondCode>(CC->getZExtValue());
----------------
dmgreen wrote:
> AArch64CC::CondCode AArch64CC = static_cast<AArch64CC::CondCode>(CSel.getConstantOperandVal(2));
done, thanks


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  https://reviews.llvm.org/D116915/new/

https://reviews.llvm.org/D116915