[llvm] f487a76 - [RISCV] Add hasStdExtZbp() to hasAndNotCompare.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2022-01-26T13:54:05-08:00
New Revision: f487a76430a0e79d017519328e808b812f8186ad

URL: https://github.com/llvm/llvm-project/commit/f487a76430a0e79d017519328e808b812f8186ad
DIFF: https://github.com/llvm/llvm-project/commit/f487a76430a0e79d017519328e808b812f8186ad.diff

LOG: [RISCV] Add hasStdExtZbp() to hasAndNotCompare.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll
    llvm/test/CodeGen/RISCV/rv64zbb-zbp.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index a01c76d587966..c71f1a698563d 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1232,7 +1232,8 @@ bool RISCVTargetLowering::hasAndNotCompare(SDValue Y) const {
   if (VT.isVector())
     return false;
 
-  return Subtarget.hasStdExtZbb() && !isa<ConstantSDNode>(Y);
+  return (Subtarget.hasStdExtZbb() || Subtarget.hasStdExtZbp()) &&
+         !isa<ConstantSDNode>(Y);
 }
 
 /// Check if sinking \p I's operands to I's basic block is profitable, because

diff  --git a/llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll b/llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll
index 68b355981e2c6..ac75dfd0773b3 100644
--- a/llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll
+++ b/llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll
@@ -580,8 +580,7 @@ define i1 @andn_seqz_i32(i32 %a, i32 %b) nounwind {
 ;
 ; RV32ZBP-LABEL: andn_seqz_i32:
 ; RV32ZBP:       # %bb.0:
-; RV32ZBP-NEXT:    and a0, a0, a1
-; RV32ZBP-NEXT:    xor a0, a0, a1
+; RV32ZBP-NEXT:    andn a0, a1, a0
 ; RV32ZBP-NEXT:    seqz a0, a0
 ; RV32ZBP-NEXT:    ret
   %and = and i32 %a, %b
@@ -636,8 +635,7 @@ define i1 @andn_snez_i32(i32 %a, i32 %b) nounwind {
 ;
 ; RV32ZBP-LABEL: andn_snez_i32:
 ; RV32ZBP:       # %bb.0:
-; RV32ZBP-NEXT:    and a0, a0, a1
-; RV32ZBP-NEXT:    xor a0, a0, a1
+; RV32ZBP-NEXT:    andn a0, a1, a0
 ; RV32ZBP-NEXT:    snez a0, a0
 ; RV32ZBP-NEXT:    ret
   %and = and i32 %a, %b

diff  --git a/llvm/test/CodeGen/RISCV/rv64zbb-zbp.ll b/llvm/test/CodeGen/RISCV/rv64zbb-zbp.ll
index dd28c772f5974..d166cbdad8875 100644
--- a/llvm/test/CodeGen/RISCV/rv64zbb-zbp.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zbb-zbp.ll
@@ -651,8 +651,7 @@ define i1 @andn_seqz_i32(i32 signext %a, i32 signext %b) nounwind {
 ;
 ; RV64ZBP-LABEL: andn_seqz_i32:
 ; RV64ZBP:       # %bb.0:
-; RV64ZBP-NEXT:    and a0, a0, a1
-; RV64ZBP-NEXT:    xor a0, a0, a1
+; RV64ZBP-NEXT:    andn a0, a1, a0
 ; RV64ZBP-NEXT:    seqz a0, a0
 ; RV64ZBP-NEXT:    ret
   %and = and i32 %a, %b
@@ -676,8 +675,7 @@ define i1 @andn_seqz_i64(i64 %a, i64 %b) nounwind {
 ;
 ; RV64ZBP-LABEL: andn_seqz_i64:
 ; RV64ZBP:       # %bb.0:
-; RV64ZBP-NEXT:    and a0, a0, a1
-; RV64ZBP-NEXT:    xor a0, a0, a1
+; RV64ZBP-NEXT:    andn a0, a1, a0
 ; RV64ZBP-NEXT:    seqz a0, a0
 ; RV64ZBP-NEXT:    ret
   %and = and i64 %a, %b
@@ -701,8 +699,7 @@ define i1 @andn_snez_i32(i32 signext %a, i32 signext %b) nounwind {
 ;
 ; RV64ZBP-LABEL: andn_snez_i32:
 ; RV64ZBP:       # %bb.0:
-; RV64ZBP-NEXT:    and a0, a0, a1
-; RV64ZBP-NEXT:    xor a0, a0, a1
+; RV64ZBP-NEXT:    andn a0, a1, a0
 ; RV64ZBP-NEXT:    snez a0, a0
 ; RV64ZBP-NEXT:    ret
   %and = and i32 %a, %b
@@ -726,8 +723,7 @@ define i1 @andn_snez_i64(i64 %a, i64 %b) nounwind {
 ;
 ; RV64ZBP-LABEL: andn_snez_i64:
 ; RV64ZBP:       # %bb.0:
-; RV64ZBP-NEXT:    and a0, a0, a1
-; RV64ZBP-NEXT:    xor a0, a0, a1
+; RV64ZBP-NEXT:    andn a0, a1, a0
 ; RV64ZBP-NEXT:    snez a0, a0
 ; RV64ZBP-NEXT:    ret
   %and = and i64 %a, %b