[PATCH] D102310: [RISCV][CodeGen] Implement IR Intrinsic support for K extension
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 26 13:40:59 PST 2022
craig.topper added inline comments.
================
Comment at: llvm/lib/Target/RISCV/RISCV.td:175
+ AssemblerPredicate<(any_of FeatureStdExtZbb, FeatureStdExtZbkb),
+ "'Zbb' (Base 'B' Instructions) or "
+ "'Zbkb' (Bitmanip instructions for Cryptography)">;
----------------
The string for Zbb was recently updated. Please update to match.
================
Comment at: llvm/test/CodeGen/RISCV/rv32zbb-zbp-zbkb.ll:9
+; RUN: llc -mtriple=riscv32 -mattr=+zbkb -verify-machineinstrs < %s \
+; RUN: | FileCheck %s -check-prefix=RV32ZBKB
----------------
Can we share a prefix for Zbb/Zbp/Zbkb?
================
Comment at: llvm/test/CodeGen/RISCV/rv64zbb-zbp-zbkb.ll:507
;
-; RV64ZBP-LABEL: andn_seqz_i32:
-; RV64ZBP: # %bb.0:
-; RV64ZBP-NEXT: and a0, a0, a1
-; RV64ZBP-NEXT: xor a0, a0, a1
-; RV64ZBP-NEXT: seqz a0, a0
-; RV64ZBP-NEXT: ret
+; RV64ZBP-ZBKB-LABEL: andn_seqz_i32:
+; RV64ZBP-ZBKB: # %bb.0:
----------------
This a bug that Zbp doesn't match Zbb. I'll fix it. You'll need to add Zbkb to RISCVTargetLowering::hasAndNotCompare in this patch.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D102310/new/
https://reviews.llvm.org/D102310
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